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- 17:14, 10 September 2025 J-Link Pro PoE V7 (hist | edit) [4,608 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link Pro PoE V7'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link PRO. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 10 MBd |- |} == Specifications == {| class="seggertable" |- ! Specifi...")
- 16:10, 10 September 2025 TI LP-MSPM0L2117 (hist | edit) [900 bytes] Torben.scharping (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the TI LP-MSPM0L2117 evaluation board.<br> 450px | thumb | right == Preparing for J-Link == *Connect the J-Link to J16. *Power the board via USB connector. * Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: File:T...")
- 09:48, 9 September 2025 Comparison SEGGER Toolchain and gcc with CMake (hist | edit) [10,479 bytes] Alexander.Uwah (talk | contribs) (Added initial version.)
- 03:39, 9 September 2025 Link register (hist | edit) [354 bytes] Rolf (talk | contribs) (Created page with "The Link register is a register which can hold the return address when calling a subroutine. The term link register is mostly used in the ARM world, in other architectures it is called RA (return address). Basically a call instruction: BL Sub // LR = PC, PC = &Sub and a return instruction BX LR // PC = LR work together as a team.")
- 01:37, 9 September 2025 ISA (hist | edit) [759 bytes] Rolf (talk | contribs) (Created page with "In computing, ISA stands for Instruction Set Architecture. It defines the instruction set of a CPU along withh its encoding. The ISA is all that is needed to develop a compiler and equally to write a simulator for a CPU compatible with this ISA. == FAQ == Q: Does the ISA define the performance?<br> A: No, not at all! Actually, it is very common to have multiple CPUs which are compatible from an ISA perspective with different performance. One CPU might have a 3 stag...")
- 11:32, 8 September 2025 Espressif ESP32-P4 (hist | edit) [1,921 bytes] Artjom.Kister (talk | contribs) (Created page with "Category:Device families {{:Template:DeviceFamily | DeviceName=ESP32-P4 | DeviceCore=RISC-V | FlashBanks= {{:Template:FlashBankTableRow | BankName=External QSPI Flash | BaseAddress=0x80000000 | JLinkSupport=no | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=- | Size=- }} }} }} ==Watchdog Handling== *The device has four watchdogs. *The watchdogs are stopped during debugging. ==Multi-Core Support== Before proceeding with this article, please check out the g...")
- 11:06, 8 September 2025 Espressif ESP32-P4 NANO (hist | edit) [1,495 bytes] Artjom.Kister (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the Espressif ESP32-P4_NANO evaluation board.<br> 450px | thumb | right == Preparing for J-Link == *Enable external JTAG interface using the following link ESP32 external JTAG interface *Connect the J-Link to this pins: {| class="seggertable" |- ! J-Link Pin || Connector !! Pin || Name |- | VTref || J1 || 1 || 3V3 |- | GND || J1 || 15 || GND |- | TDI || J1 |...")
- 02:51, 8 September 2025 Push instruction (hist | edit) [767 bytes] Rolf (talk | contribs) (Created page with "The push instruction places (pushes) data onto the stack. ==Overview== The PUSH instruction is an instruction that can be found in almost all CPUs. It is used to place data onto the stack. In most CPU architectures, the stack is a region of memory that operates in a last-in, first-out (LIFO) manner. The PUSH instruction is used to store register values, return addresses, or other data onto the stack. ==Functionality== When the PUSH instruction is executed,...")
- 02:44, 8 September 2025 RET Instruction (hist | edit) [633 bytes] Rolf (talk | contribs) (Created page with "RET Instruction The RET (Return) instruction is an instruction found in almost all CPUs. It is used to return from a subroutine or function call. ==Overview== When a function or subroutine finishes, the RET instruction tells the processor to return to the caller, meaning to jump back to the instruction immediately following the original call. ==Functionality== In most architectures, when a function is called, the address of the next instruction is pushed onto the stack....")
- 18:58, 7 September 2025 S32E (hist | edit) [582 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base S32 is a virtual CPU designed, implemented and heavily used by SEGGER. It is used in the Flasher family of in-system programmers, the J-Link & J-Trace debug and trace probes and available for licensing as emApp, along with documentation and development environment / compiler.")
- 16:28, 6 September 2025 virtual CPU (hist | edit) [5,023 bytes] Rolf (talk | contribs) (Created page with "A virtual CPU is a CPU implemented in software. It has an executor which runs on a real (host) CPU.")
- 14:11, 5 September 2025 Renesas MCB-RA8T2 (hist | edit) [820 bytes] Dennis.Griebler (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the Renesas EK-RA8T2 evaluation board.<br> 450px | thumb | right == Preparing for J-Link == *Connect the J-Link to CN10 *Power the board via USB-C * Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: File:Renesas_MCB-RA8T2_connect.png|400px...")
- 08:49, 5 September 2025 Flasher - Troubleshooting (hist | edit) [3,773 bytes] Leon (talk | contribs) (Created page with "The connection to a Flasher or the target device may not work for a variety of reasons.<br> The following article provides information on how to troubleshoot and fix these connectivity issues.<br> __TOC__ == Generic == # Make sure to use the most recent version of the Flasher software, available for download [https://www.segger.com/downloads/flasher/ here]. # Make sure that Flasher is running its most recent firmware version. For more information on Flasher firmware,...")
- 10:35, 4 September 2025 TI CC2340 Password Authentication (hist | edit) [2,363 bytes] Simon Buchholz (talk | contribs) (Created page with "Category:Device families The TI CC2340 series of comes with a security feature called Password Protection. SEGGER implemented support for this feature via a dedicated utility called Device Provisioner. For more information about this, please refer to the Device Provisioner article. CC2340 Password Protection features are implemented in the PCode_DevPro_TI_CC2340_PasswordAuth.pex script file. __TOC__ == Important notes == #Password protectio...")
- 10:21, 4 September 2025 Silicon Labs EFM32xG26 (hist | edit) [2,795 bytes] Joel.Steffens (talk | contribs) (Created page with "Category:Device families The '''Silicon Labs EFM32xG26''' are SoCs based on Cortex-M33 microcontrollers. They are compatible to the Silicon Labs EFR32xG26 device family. These MCUs are part of the EFx32 Series 2 devices. __TOC__ == EFx32 Series 2 specifics == Please refer to the Silicon Labs EFx32 Series 2 article. ==Flash Banks== ===EFM32xG26xxxF1024=== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableR...")
- 10:06, 4 September 2025 TI LP-MSPM0G5117 (hist | edit) [858 bytes] Torben.scharping (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the [TI LP-MSPM0G5117 evaluation board.<br> '''[PICTURE OF BOARD]''' 450px == Preparing for J-Link == *Connect the J-Link to ...... *Connect the J-Link to this pins: {| class="seggertable" |- ! J-Link Pin || Connector !! Pin || Name |- | VTref || || || |- | GND || || || |- | nTRST || || || |- | TDI || || || |- | TMS/SWDIO || || || |- | TCK/SWCLK || || || |- |...")
- 14:47, 3 September 2025 EFM32PG26 Pro Kit (hist | edit) [934 bytes] Joel.Steffens (talk | contribs) (Created page with "Category:Evalboards thumb | right | 250 px The '''EFM32PG26 Pro Kit''' is an Silicon Labs EFM32PG26 evaluation board. __TOC__ == Preparing for J-Link == There is an onboard debugger (J-Link OB) available on this board. * Connect the "DBG USB" to power the board and connect the J-Link OB. * Power on the board by setting the "PWR" switch to "DBG USB" (left). * Verify the Connection with [https://wiki.segger.com/J-Link_cannot_con...")
- 14:40, 3 September 2025 EFM32PG26 Explorer Kit (hist | edit) [949 bytes] Joel.Steffens (talk | contribs) (Created page with "Category:Evalboards thumb | right | 250 px The '''EFM32PG26 Explorer Kit''' is an Silicon Labs EFM32PG26 evaluation board. __TOC__ == Preparing for J-Link == There is an onboard debugger (J-Link OB) available on this board. * Connect the "DBG USB" to power the board and connect the J-Link OB. * Power on the board by setting the "PWR" switch to "DBG USB" (left). * Verify the Connection with [https://wiki.segger.com/J-Link_...")
- 08:45, 3 September 2025 Renesas RA8T2 (hist | edit) [3,619 bytes] Dennis.Griebler (talk | contribs) (Created page with "Category:Device families The '''Renesas RA8T2''' are Cortex-M85 based microcontrollers with optional second Cortex-M33 core. __TOC__ ==Flash Banks== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=MRAM (Secure) | BaseAddress=0x02000000 | JLinkSupport=yes | NumOfLoaders=2 | Loader= {{:Template:FlashLoader | Name=Default | Size=up to 1 MB }} {{:Template:FlashLoader | Name=RAMLess | Size=up to 1 MB }} }} {{:Template:FlashBankTabl...")
- 13:49, 2 September 2025 Renesas FPB-RA0L1 (hist | edit) [826 bytes] Joel.Steffens (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the Renesas FPB-RA0L1 evaluation board.<br> 450px == Preparing for J-Link == *Connect USB-C cable to on-board J-Link (J10) * Verify the Connection with e.g. [https://wiki.segger.com/J-Link_cannot_connect_to_the_CPU#Verify_functionality_using_J-Link_Commander J-Link Commander]. The output should look as follows: 400px == Exa...")
- 13:46, 2 September 2025 Renesas RA0L1 (hist | edit) [1,168 bytes] Joel.Steffens (talk | contribs) (Created page with "Category:Device families The '''Renesas RA0L1''' are Cortex-M23 based microcontrollers. __TOC__ ==Internal Flash== {| class="seggertable" |- ! Flash Bank || Base address !! Size || J-Link Support || Loaders |- | Program flash || 0x00000000 || Up to 64 KB || style="text-align:center;"| {{YES}} || *Default |- | Data flash || 0x40100000 || 1 KB || style="text-align:center;"| {{YES}} || *Default<br> |} '''NOTE:'''The device has an Independent Watchdog Timer (IWDT) whic...")
- 02:03, 2 September 2025 MMU (hist | edit) [1,344 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base A Memory Management Unit (MMU) is a hardware component of a processor that translates virtual addresses into physical addresses. It also manages memory protection and cache control, enabling features such as virtual memory, process isolation, and efficient system memory usage. ==Overview== The MMU sits between the CPU and main memory. Every time the CPU issues a memory access, the MMU translates the virtual address used by software into the...")
- 17:10, 1 September 2025 How to find the lock for your software license (hist | edit) [944 bytes] Johannes (talk | contribs) (Created page with "License activation keys for SEGGER software tools are usually locked to a computer, identified by its Ethernet/WiFi MAC address. This MAC address needs to be provided on license requests and license purchases. == Find the MAC address in Embedded Studio == * Open Embedded Studio. * Go to Tools -> License Manager... -> Diagnose Problems. * Pick one of the displayed MAC addresses, which belongs to a physical network adapter. == Find the MAC address in Ozone == * Open Oz...")
- 11:47, 1 September 2025 Silicon Labs BRD4412A (hist | edit) [1,074 bytes] Niklas.Lennartz (talk | contribs) (Created page.)
- 11:27, 1 September 2025 Silicon Labs EFR32xG29 (hist | edit) [1,246 bytes] Niklas.Lennartz (talk | contribs) (Created page.)
- 22:10, 31 August 2025 Flash memory (hist | edit) [789 bytes] Rolf (talk | contribs) (Created page with "Flash Memory Flash memory is a type of non-volatile storage that retains data even when the power is turned off. It is widely used in embedded systems for storing firmware, configuration data, and user settings. Flash memory can be electrically erased and reprogrammed in blocks, making it very flexible for iterative updates. In SEGGER’s ecosystem, flash memory is often managed and programmed using tools like J-Link debug probes and Flasher programmers, which support...")
- 21:43, 31 August 2025 Hardcore (hist | edit) [2,360 bytes] Rolf (talk | contribs) (Created page with "Hardcore CPU A hardcore CPU (also called hard IP) is a processor that is permanently implemented in silicon. Unlike softcores, which run in programmable logic (typically FPGAs), a hardcore CPU is a fixed part of the chip, designed and verified at the transistor level by the semiconductor manufacturer. ==Overview== Hardcores are also typically delivered to the silicon vendor in synthesizable HDL code (usually Verilog), similar to softcores. The hardcore is then synt...")
- 19:56, 31 August 2025 SP (hist | edit) [623 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base The stack pointer is an essential part of almost any CPU design. It points to a location in RAM used to store (push) or retrieve (pop) information from. On most CPUs, the Stack grows downwards, so a push operation decrements the SP, but there are also implementation where the stack grows, so a push increments the SP. When saying "incrementing" or decrementing, it should be noted that the SP usually handles items that are multiples of the proce...")
- 19:49, 31 August 2025 Speedy (hist | edit) [678 bytes] Rolf (talk | contribs) (Created page with "Speedy is the name for SEGGER's softcore used in many of their J-Link and Flasher products. Speedy is an 8-bit core, designed to be lean and as fast as possible, with a rather basic instruction set. It execute one instruction per cycle (with the exception of branch instructions) and is used as interface processor. In most cases, it runs at 200MHz, providing an accurate 5ns timing which is more than efficient for most debug and programming interfaces. On AMD Ultrascale si...")
- 18:34, 31 August 2025 Softcore (hist | edit) [665 bytes] Rolf (talk | contribs) (Created page with "SoftCore A SoftCore (or soft processor core) is a processor design described in a hardware description language (HDL), such as VHDL or Verilog, and implemented on programmable logic (e.g., an FPGA). Unlike a HardCore processor fixed in silicon, a SoftCore is flexible and reconfigurable, allowing customization, extensions, or multiple instances in the same device. Examples include MicroBlaze, Nios II, and RISC-V soft cores.")
- 16:20, 31 August 2025 flashloader (hist | edit) [243 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base A Flash loader is a (typically small) programmer which programs the flash of a microcontroller (or SoC). It is loaded into the RAM of the device, and is then given the data to be programmed, usually in small chunks.")
- 05:40, 31 August 2025 ISP (hist | edit) [71 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base ISP is short for In-system programming.")
- 05:38, 31 August 2025 SR (hist | edit) [643 bytes] Rolf (talk | contribs) (Created page with "In the context of an Embedded system, SR usually stands for status register. The status register is a CPU register which consists of a collection of flags and settings. Which flags and which settings depends very much on the CPU. == Flags == Which Flags a CPU depends. However, there are a number of flags which most CPUs have, such as: Z-Flag Zero Flag. Indicates if the result of the previous operation has been 0 C-Flag Carry Flag. Typically used in shift and rotate ope...")
- 01:52, 31 August 2025 RETI (hist | edit) [571 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base RETI is short for RETurn from Interrupt. It is the name of the instruction that many CPUs use as a last instruction in an Interrupt Service Routine (ISR). RETI does not exist on all CPUs, or it has a different name, but RETI seems most common. What it does is usually restore the Program Counter (PC) and the flag register. It usually does the exact opposite of what happens when entering an ISR. So if the CPU saves 8 registers when enter...")
- 20:20, 30 August 2025 PLL (hist | edit) [138 bytes] Rolf (talk | contribs) (Created page with "A phase-locked loop is a piece of hardware that generates an output signal whose frequency is typically a multiple of the input frequency.")
- 20:16, 30 August 2025 Timer (hist | edit) [457 bytes] Rolf (talk | contribs) (Created page with "In computing and in embedded systems, a timer (also known as programmable interval timer (PIT)) is a counter that generates an output signal when it reaches a programmed count. The output signal can trigger an interrupt. Timers can be up or down counting, and in many cases can be programmed to be single shot or multiple shot or simply continue once it has read the programmed count (or 0 in case of a down counter)")
- 20:10, 30 August 2025 DMA (hist | edit) [2,053 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base In embedded systems, ore more generally in computer systems, DMA stands for Direct memory access. Direct memory access is the ability of a peripheral, such as an Ethernet or USB controller to read or write data directly to/from memory, without involving the CPU. == Overview == DMA requires a DMA controller, which can be a part of the peripheral. == Benfits == A DMA can usually perform the transfer faster than the CPU,...")
- 19:21, 30 August 2025 MCU (hist | edit) [115 bytes] Rolf (talk | contribs) (Created page with "MCU is short for Microcontroller Unit, or even shorter Microcontroller. Please click on the link to learn more.")
- 17:42, 30 August 2025 In-system programming (hist | edit) [4,491 bytes] Rolf (talk | contribs) (Created page with "Category:Knowledge Base In-system programming, also known as ISP or in-circuit programming (ICP), is the process of programming a computer chip in system, so when it has already been soldered (connected) to a printed circuit board. Almost all devices with some sort of non-volatile storage can be programmed in-system. This applies to microcontrollers (MCUs), FPGAs (Field programmables gate arrays) as well as typically serial (Q)SPI flashes. Even other types of flashes...")
- 16:45, 29 August 2025 SinoWealth SH32F26 (hist | edit) [1,058 bytes] Simon Buchholz (talk | contribs) (Created page with "Category:Device families __TOC__ The '''SinoWealth SH32F26''' series are microcontrollers based on the Arm® STAR processor.<br> ==Flash Banks== ===Internal Flash=== {| class="seggertable" |- ! Device || Base address !! Size || J-Link Support |- | Code Area || 0x00000000|| 64 KB || {{YES}} |- | E2PROM || 0x0FFC0000|| 4 KB || {{YES}} |- | Code Protection || 0x0FFF8000|| 1 KB || {{YES}} |- | Code Option || 0x0FFFA000|| 1 K...")
- 17:51, 27 August 2025 J-Link PRO PoE V6 (hist | edit) [4,612 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link PRO PoE V6'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link PRO. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 10 MBd |- |} == Specifications == {| class="seggertable" |- ! Specifi...")
- 17:37, 27 August 2025 J-Link WiFi V2 (hist | edit) [4,343 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link WiFi V2'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link WiFi. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 115200 Bd <sup>[1]</sup> |- |} {{Note|1=<sup>'''[1]'''</sup> {{JLinkVCO...")
- 17:31, 27 August 2025 J-Link PLUS Compact V13 (hist | edit) [4,157 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link PLUS Compact V13'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link PLUS. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 115200 Bd <sup>[1]</sup> |- |} {{Note|1=<sup>'''[1]'''</sup> {...")
- 17:30, 27 August 2025 J-Link PLUS V13 (hist | edit) [4,155 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link PLUS V13'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link PLUS. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 115200 Bd <sup>[1]</sup> |- |} {{Note|1=<sup>'''[1]'''</sup> {{JLinkVC...")
- 17:25, 27 August 2025 J-Link BASE Compact V13 (hist | edit) [4,157 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link BASE Compact V13'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link BASE. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 115200 Bd <sup>[1]</sup> |- |} {{Note|1=<sup>'''[1]'''</sup> {...")
- 17:21, 27 August 2025 J-Link BASE V13 (hist | edit) [4,155 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link BASE V13'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link BASE. __TOC__ == Interface speeds == {| class="seggertable" |- ! Interface !! Max. speed |- || VCOM || 115200 Bd <sup>[1]</sup> |- |} {{Note|1=<sup>'''[1]'''</sup> {{JLinkVC...")
- 17:14, 27 August 2025 J-Link EDU Mini V1 (hist | edit) [2,752 bytes] Theodor.fischer (talk | contribs) (Created page with "This page contains the mechanical and electrical specifications of the SEGGER '''J-Link EDU Mini V2'''. <br> For information on the general specifications as well as an overview of supported software features refer to J-Link EDU. == Specifications == {| class="seggertable" |- ! Specification !! Value |- !colspan="2"| General |- | Supported OS || Microsoft Windows (x86/x64), Linux (x86/x64), macOS (x86) |- | El...")
- 16:04, 27 August 2025 Nations N32H762IIL7 STB (hist | edit) [1,129 bytes] Artjom.Kister (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the Nations N32H762IIL7_STB evaluation board.<br> 450px == Preparing for J-Link == *Connect the J-Link to this pins: {| class="seggertable" |- ! J-Link Pin || Connector !! Pin || Name |- | VTref || J11 || 2 || VDD |- | GND || J11 || 16 || GND |- | TMS/SWDIO || J11 || 4 || PA13 |- | TCK/SWCLK || J11 || 6 || PA14 |- | RESET || J11 || 12 || NRST |- |} *Power the...")
- 16:00, 27 August 2025 Nations N32H760VIB7 STB (hist | edit) [1,128 bytes] Artjom.Kister (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the Nations N32H760VIB7_STB evaluation board.<br> 450px == Preparing for J-Link == *Connect the J-Link to this pins: {| class="seggertable" |- ! J-Link Pin || Connector !! Pin || Name |- | VTref || J9 || 1 || VDD |- | GND || J9 || 16 || GND |- | TMS/SWDIO || J9 || 4 || SWDIO |- | TCK/SWCLK || J9 || 6 || SWDCLK |- | RESET || J9 || 12 || RESET |- |} *Power the...")
- 10:52, 27 August 2025 Nations N32H787XKB7 STB (hist | edit) [1,127 bytes] Artjom.Kister (talk | contribs) (Created page with "Category:Evalboards __TOC__ This article describes specifics for the Nations N32H787XKB7_STB evaluation board.<br> 450px == Preparing for J-Link == *Connect the J-Link to this pins: {| class="seggertable" |- ! J-Link Pin || Connector !! Pin || Name |- | VTref || J11 || 2 || VDD |- | GND || J11 || 16 || GND |- | TMS/SWDIO || J11 || 4 || PA13 |- | TCK/SWCLK || J11 || 6 || PA14 |- | RESET || J11 || 12 || NRST |- |} *Power the...")
