User contributions for Rolf

9 September 2025

• 03:3903:39, 9 September 2025 diff hist +354‎ N Link register ‎ Created page with "The Link register is a register which can hold the return address when calling a subroutine. The term link register is mostly used in the ARM world, in other architectures it is called RA (return address). Basically a call instruction: BL Sub // LR = PC, PC = &Sub and a return instruction BX LR // PC = LR work together as a team." current
• 01:3701:37, 9 September 2025 diff hist +759‎ N ISA ‎ Created page with "In computing, ISA stands for Instruction Set Architecture. It defines the instruction set of a CPU along withh its encoding. The ISA is all that is needed to develop a compiler and equally to write a simulator for a CPU compatible with this ISA. == FAQ == Q: Does the ISA define the performance?<br> A: No, not at all! Actually, it is very common to have multiple CPUs which are compatible from an ISA perspective with different performance. One CPU might have a 3 stag..." current

8 September 2025

• 21:3921:39, 8 September 2025 diff hist +182‎ m virtual CPU ‎ →‎Overview current
• 21:3721:37, 8 September 2025 diff hist +10‎ m virtual CPU ‎ →‎FAQ
• 21:3621:36, 8 September 2025 diff hist +642‎ m virtual CPU ‎No edit summary
• 21:2821:28, 8 September 2025 diff hist +4‎ m virtual CPU ‎ →‎Code density
• 21:2821:28, 8 September 2025 diff hist +32‎ m virtual CPU ‎ →‎Code density
• 21:2521:25, 8 September 2025 diff hist +502‎ m virtual CPU ‎No edit summary
• 21:2321:23, 8 September 2025 diff hist +27‎ m virtual CPU ‎ →‎Examples
• 02:5102:51, 8 September 2025 diff hist +767‎ N Push instruction ‎ Created page with "The push instruction places (pushes) data onto the stack. ==Overview== The PUSH instruction is an instruction that can be found in almost all CPUs. It is used to place data onto the stack. In most CPU architectures, the stack is a region of memory that operates in a last-in, first-out (LIFO) manner. The PUSH instruction is used to store register values, return addresses, or other data onto the stack. ==Functionality== When the PUSH instruction is executed,..." current
• 02:4602:46, 8 September 2025 diff hist +4‎ m Call Instruction ‎ →‎Push PC current
• 02:4502:45, 8 September 2025 diff hist +1‎ m Call Instruction ‎ →‎Push PC
• 02:4402:44, 8 September 2025 diff hist +633‎ N RET Instruction ‎ Created page with "RET Instruction The RET (Return) instruction is an instruction found in almost all CPUs. It is used to return from a subroutine or function call. ==Overview== When a function or subroutine finishes, the RET instruction tells the processor to return to the caller, meaning to jump back to the instruction immediately following the original call. ==Functionality== In most architectures, when a function is called, the address of the next instruction is pushed onto the stack...." current
• 02:3902:39, 8 September 2025 diff hist +605‎ m Call Instruction ‎ →‎Push PC
• 02:3302:33, 8 September 2025 diff hist +662‎ m Call Instruction ‎No edit summary
• 01:5501:55, 8 September 2025 diff hist +845‎ m Call Instruction ‎No edit summary

7 September 2025

• 19:0119:01, 7 September 2025 diff hist +274‎ m S32E ‎No edit summary current
• 18:5818:58, 7 September 2025 diff hist +308‎ N S32E ‎ Created page with "Category:Knowledge Base S32 is a virtual CPU designed, implemented and heavily used by SEGGER. It is used in the Flasher family of in-system programmers, the J-Link & J-Trace debug and trace probes and available for licensing as emApp, along with documentation and development environment / compiler."
• 18:5518:55, 7 September 2025 diff hist +28‎ m virtual CPU ‎No edit summary
• 18:5218:52, 7 September 2025 diff hist −28‎ m virtual CPU ‎ →‎FAQ
• 16:4616:46, 7 September 2025 diff hist +602‎ m virtual CPU ‎No edit summary
• 16:0816:08, 7 September 2025 diff hist +10‎ m virtual CPU ‎ →‎Examples
• 16:0616:06, 7 September 2025 diff hist +2,778‎ m virtual CPU ‎No edit summary

6 September 2025

• 17:5717:57, 6 September 2025 diff hist +135‎ m virtual CPU ‎No edit summary
• 17:5517:55, 6 September 2025 diff hist +15‎ m CPU ‎ →‎CPU implementations current
• 16:2816:28, 6 September 2025 diff hist +99‎ N virtual CPU ‎ Created page with "A virtual CPU is a CPU implemented in software. It has an executor which runs on a real (host) CPU."
• 15:5715:57, 6 September 2025 diff hist +43‎ m Sweet 16 ‎No edit summary current
• 15:1515:15, 6 September 2025 diff hist −3‎ m 6502 ‎ →‎Sweet 16 current

2 September 2025

• 23:0223:02, 2 September 2025 diff hist +18‎ m In-system programming ‎ →‎Overview current
• 23:0123:01, 2 September 2025 diff hist +20‎ m In-system programming ‎ →‎Overview
• 23:0023:00, 2 September 2025 diff hist +1,026‎ m Flash Memory ‎No edit summary current
• 22:3822:38, 2 September 2025 diff hist −39‎ m In-system programming ‎ →‎Overview
• 05:3405:34, 2 September 2025 diff hist +960‎ m ROM ‎No edit summary current
• 05:2505:25, 2 September 2025 diff hist +20‎ m RTT ‎No edit summary current
• 02:0302:03, 2 September 2025 diff hist +1,344‎ N MMU ‎ Created page with "Category:Knowledge Base A Memory Management Unit (MMU) is a hardware component of a processor that translates virtual addresses into physical addresses. It also manages memory protection and cache control, enabling features such as virtual memory, process isolation, and efficient system memory usage. ==Overview== The MMU sits between the CPU and main memory. Every time the CPU issues a memory access, the MMU translates the virtual address used by software into the..." current
• 01:5401:54, 2 September 2025 diff hist +208‎ m Cache ‎No edit summary current
• 01:5001:50, 2 September 2025 diff hist +198‎ m Cache ‎ →‎Cache maintenance operations
• 01:4801:48, 2 September 2025 diff hist −166‎ m Cache ‎ →‎Write back
• 01:4701:47, 2 September 2025 diff hist −6‎ m Cache ‎ →‎Write through
• 01:4501:45, 2 September 2025 diff hist +2‎ m Cache ‎ →‎Overview
• 01:4301:43, 2 September 2025 diff hist +7‎ m Cache ‎ →‎Cache lines
• 01:4001:40, 2 September 2025 diff hist +275‎ m Cache ‎ →‎Write back
• 01:3801:38, 2 September 2025 diff hist +382‎ m Cache ‎ →‎Cache maintenance operations
• 01:3601:36, 2 September 2025 diff hist +923‎ m Cache ‎ →‎Read-write (data) cache
• 01:3001:30, 2 September 2025 diff hist +357‎ m Cache ‎ →‎Read-only cache
• 00:5000:50, 2 September 2025 diff hist +94‎ m Cache ‎No edit summary
• 00:4900:49, 2 September 2025 diff hist +270‎ m Cache ‎No edit summary
• 00:2900:29, 2 September 2025 diff hist +30‎ m BASIC programming language ‎No edit summary current

1 September 2025

• 23:0123:01, 1 September 2025 diff hist −28‎ m Test Farm ‎No edit summary current

31 August 2025

• 22:1422:14, 31 August 2025 diff hist +4‎ m Flash memory ‎No edit summary current