J-Link WiFi V2
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This page contains the mechanical and electrical specifications of the SEGGER J-Link WiFi V2.
For information on the general specifications as well as an overview of supported software features refer to J-Link WiFi.
Interface speeds
| Interface | Max. speed |
|---|---|
| VCOM | 115200 Bd [1] |
Note:
[1] The max. baudrate for J-Link depends on the configured Eco mode:
| Eco mode | Max. baudrate |
|---|---|
| Normal | 115200 Bd |
| Eco | 57600 Bd |
| Eco Plus | 28800 Bd |
| Eco Max | 28800 Bd |
Specifications
| Specification | Value |
|---|---|
| General | |
| Supported OS | Microsoft Windows (x64/Arm), Linux (x64/Arm), macOS (x64/Apple Silicon) |
| Electromagnetic compatibility (EMC) | EN 301 489-1/-17, EN 300 328, EN 62368 |
| Operating temperature | +5°C ... +60°C |
| Storage temperature | -20°C ... +65°C |
| Relative humidity (non-condensing) | Max. 90% rH |
| Mechanical | |
| Size (without cables) | 103mm x 53mm x 28mm |
| Weight (without cables) | 70g |
| Available interfaces | |
| WiFi interface | IEEE 802.11 b/g/n (2.4 GHz) |
| USB interface | USB 2.0 (Hi-Speed); USB Type B |
| Target interface | JTAG 20-pin (14-pin and other adapters available) |
| JTAG/SWD Interface, Electrical | |
| Power supply | USB powered, max. 220mA@5V |
| Target interface voltage (VIF) | 1.2V ... 5V |
| Current drawn from target voltage sense pin (VTRef) | < 25µA |
| Target supply voltage | 5V (derived from USB voltage) |
| Target supply current | Max. 300mA |
| Reset Type | Open drain. Can be pulled low or tristated. |
| Reset low level output voltage (VOL) | VOL <= 10% of VIF |
| For the whole target voltage range (1.2V <= VIF <= 5V) | |
| LOW level input voltage (VIL) | VIL <= 40% of VIF |
| HIGH level input voltage (VIH) | VIH >= 60% of VIF |
| For 1.2V <= VIF <= 3.6V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
| For 3.6V <= VIF <= 5V | |
| LOW level output voltage (VOL) with a load of 10 kOhm | VOL <= 20% of VIF |
| HIGH level output voltage (VOH) with a load of 10 kOhm | VOH >= 80% of VIF |
| JTAG/SWD Interface, Timing | |
| Target interface speed | Max. 15 MHz |
| SWO sampling frequency | Max. 30 MHz |
| Data input rise time (Trdi) | Trdi <= 20ns |
| Data input fall time (Tfdi) | Tfdi <= 20ns |
| Data output rise time (Trdo) | Trdo <= 10ns |
| Data output fall time (Tfdo) | Tfdo <= 10ns |
| Clock rise time (Trc) | Trc <= 3ns |
| Clock fall time (Tfc) | Tfc <= 3ns |