Speedy

Speedy is the name for SEGGER's softcore used in many of their J-Link and Flasher products. Speedy is an 8-bit core, designed to be lean and as fast as possible, with a rather basic instruction set. It executes one instruction per cycle (with the exception of branch instructions) and is used as interface processor. In most cases, it runs at 200MHz, providing an accurate 5ns timing which is more than efficient for most debug and programming interfaces. On AMD Ultrascale silicon, it can run at speeds of 500MHz and more. Since it uses very little logic, multiple instances can easily be implemented on a single FPGA, such as using one Speedy for sending and one for receiving.

Basic information

Below is a list with some basic information about the Speedy module:

• 32 general-purpose registers
• All instructions are 16-bit
• Instructions are executed in a single cycle, except for branches, which require three cycles if the branch is taken
• After reset, Speedy starts execution at location zero, the first instruction loaded into Speedy
• Single-level return stack used with JSR and RET instructions
• No multiplier or divider
• No RAM and therefore no stack pointer and no push or pop instructions
• No interrupts

Registers

Speedy contains the following registers:

• Rx - 8 bits 32 General purpose registers (R0 .. R31)
• Flags: Zero and Carry bits
• PC - 10 bits Program counter
• RA 10 bits Return address register (internal, used implicitly by the JSR and RET instructions)
• D - 16 bits Delay register (internal, used by Delay instruction which provides cycle-accurate delays)

Communicating with Speedy

Speedy is "just" an interface coprocessor, so it does require a main processor. For communication with the main processor, two FIFO buffers are used:
An up buffer for sending data from Speedy to the main CPU, and a down buffer for sending data back.

Speedy can send and receive data via the I/O space, which contains 8-bit registers used to place a byte in the up buffer (OUT_TX_DATA) and fetch a byte from the down buffer (IN_RX_DATA). To ensure that the data is placed in the up buffer only when it is not full, the IN_TX_STAT register must be checked. The IN_RX_STAT register must be used to check if the Programming App has placed some data in the down buffer. The following assembly code waits for data from the Master CPU echoes it back.

//
// Peripheral addresses. Not part of Speedy itself.
//
OUT_TX_DATA = 0x3E
IN_TX_STAT = 0x3D
IN_RX_DATA = 0x3E
IN_RX_STAT = 0x3F

// **********************************************************************
// *
// * Program start
// *
Start:
  //
  // Wait for input data
  //
  WWL IN_RX_STAT      // Wait-while-low, so until data is in buffer
  //
  // Fetch the data.
  //
  IN R0, IN_RX_DATA
  //
  // Wait until there's free space in the output buffer. If one knows that this is the case, this step can be omitted
  //
  WWH IN_TX_STAT      // wait-while-high, so until there is space in output buffer
  //
  // Send the received data back to the flash loader.
  //
  OUT R0, OUT_TX_DATA
  //
  // Jump to start.
  //
  JMP Start

FAQ

Q: Is Speedy open source?
A: No, it is proprietary technology developed, owned and used by SEGGER

Q: Can Speedy be used to emulate a UART?
A: Yes, easily. It only takes about 30 instructions to emulate a UART. Typically, for UARTs, one Speedy is used for Rx and one is used for Tx.

Q: When Speedy is used to emulate a UART, what is the maximum speed possible?
A: Maximum speed (when running at 200MHz) is 50MBaud, which is usually more than the required.

Q: When Speedy is used to emulate a UART, can it also do parity and stop bits?
A: Yes, easily. That is the big advantage of doing things in software: Modifying the program given to Speedy can do the trick easily.

Q: Can Speedy be cast in silicon as a hardcore?
A: We have not tried it, but see no reason why it would not.

Q: Which language is Speedy written in?
A: Verilog

Q: How is Speedy programmed?
A: The program is written in Speedy ASM language, which is pretty straightforward.

Q: Is a C-compiler available for Speedy?
A: No. Speedy is too simple to be programmed in C. Besides, one would lose the advantage of exact timing.

Q: How is the program given to Speedy?
A: Typically, Speedy's program memory can be written to by the main processor.