NXP MCX A

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The NXP MCX A are single core ARM Cortex-M33 microprocessors.

Flash Banks

MCX A173

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Internal Flash 0x00000000 YES.png YES.png Default 120 KB
CMPA[1] 0x001E0000 YES.png YES.png Default 8 KB
  1. ↑ See CMPA

MCX A174

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Internal Flash 0x00000000 YES.png YES.png Default 248 KB
CMPA[1] 0x003E0000 YES.png YES.png Default 8 KB
  1. ↑ See CMPA

MCX A175/A185/A255/A345/A355

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Internal Flash 0x00000000 YES.png YES.png Default 504 KB
CMPA[1] 0x007E0000 YES.png YES.png Default 8 KB
  1. ↑ See CMPA

MCX A176/A186/A256/A346/A356

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Internal Flash 0x00000000 YES.png YES.png Default 1016 KB
CMPA[1] 0x00FE0000 YES.png YES.png Default 8 KB
  1. ↑ See CMPA

MCX A265/A365

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Internal Flash 0x00000000 YES.png YES.png Default 448 KB
Secure Installer[1] 0x00070000 YES.png YES.png Default 56 KB
CMPA[2] 0x007E0000 YES.png YES.png Default 8 KB
  1. ↑ Secure Installer has to be deleted in order to program this area.
  2. ↑ See CMPA

MCX A266/A366

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Internal Flash 0x00000000 YES.png YES.png Default 960 KB
Secure Installer[1] 0x000F0000 YES.png YES.png Default 56 KB
CMPA[2] 0x00FE0000 YES.png YES.png Default 8 KB
  1. ↑ Secure Installer has to be deleted in order to program this area.
  2. ↑ See CMPA

MCX A577/A567/A566/A557/A556/A537/A536/A457/A456/A287/A286

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
Program Flash (NS) 0x00000000 YES.png YES.png Default Up to 2 MB
Program Flash (S) 0x10000000 YES.png YES.png Default Up to 2 MB
FlexSPI (NS)[1] 0x08000000 YES.png YES.png PortA1 Up to 128 MB
PortA2 Up to 128 MB
PortB1 Up to 128 MB
PortB2 Up to 128 MB
FlexSPI (S)[1] 0x18000000 YES.png YES.png PortA1 Up to 128 MB
PortA2 Up to 128 MB
PortB1 Up to 128 MB
PortB2 Up to 128 MB
FlexSPI (NS)[1] 0x80000000 YES.png YES.png PortA1 Up to 256 MB
PortA2 Up to 256 MB
PortB1 Up to 256 MB
PortB2 Up to 256 MB
FlexSPI (S)[1] 0x90000000 YES.png YES.png PortA1 Up to 256 MB
PortA2 Up to 256 MB
PortB1 Up to 256 MB
PortB2 Up to 256 MB


  1. ↑ 1.0 1.1 1.2 1.3 QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
    J-Link supports multiple pin configurations. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.

The FlexSPI interface supports two ports (port A and port B). Each port supports up to two flash devices by providing two chip select outputs.
J-Link supports the following four pin configuration for FlexSPI flash programming:

Port A Port B
Port A1 Port A2 Port B1 Port B2
Signal Pin Signal Pin Signal Pin Signal Pin
FLEXSPI0_A_SS0_b P3_0 FLEXSPI0_A_SS1_b P3_1 FLEXSPI0_B_SS0_b P3_17 FLEXSPI0_B_SS1_b P3_6
FLEXSPI0_A_SCLK P3_7 FLEXSPI0_A_SCLK P3_7 FLEXSPI0_B_SCLK P3_16 FLEXSPI0_B_SCLK P3_16
FLEXSPI0_A_DATA0 P3_8 FLEXSPI0_A_DATA0 P3_8 FLEXSPI0_B_DATA0 P3_15 FLEXSPI0_B_DATA0 P3_15
FLEXSPI0_A_DATA1 P3_9 FLEXSPI0_A_DATA1 P3_9 FLEXSPI0_B_DATA1 P3_14 FLEXSPI0_B_DATA1 P3_14
FLEXSPI0_A_DATA2 P3_10 FLEXSPI0_A_DATA2 P3_10 FLEXSPI0_B_DATA2 P3_13 FLEXSPI0_B_DATA2 P3_13
FLEXSPI0_A_DATA3 P3_11 FLEXSPI0_A_DATA3 P3_11 FLEXSPI0_B_DATA3 P3_12 FLEXSPI0_B_DATA3 P3_12
FLEXSPI0_A_DQS P3_6 FLEXSPI0_A_DQS P3_6 FLEXSPI0_B_DQS P3_1 FLEXSPI0_B_DQS P3_1

ECC Flash

  • Device has ECC Flash, but no special handling required.

Secure Installer

  • Some derivatives come with a secure installer(SI).
  • The secure installer can be deleted by the Device Provisioner: MCX A SiErase .
  • When this secure installer is removed, a device unique token is present in the CMPA area.
Warning:
This device unique token has to be has to be resident forever in the CMPA area, otherwise the device will be bricked.

CMPA

  • CMPA area contains device configuration data.
  • Not correct programmed data may brick the device.

Watchdog Handling

  • The device has up to two WWDT and CDOG watchdogs.
  • The WWDT watchdogs are fed during flash programming.
  • No handling for CDOG watchdogs implemented.

Device Specific Handling

Reset

  • The J-Link performs a device specific reset sequence. SRAM and Flash is set to RWX.
  • On MCX A2TS devices, the Analog Glitch Detector (aGDET) and Digital Glitch Detector (dGDET) are temporarily disabled prior to issuing a system reset or initiating a flash programming operation. Any modifications to aGDET and dGDET settings are restored after the operation completes.

Attach

Attach is supported.

Evaluation Boards

Example Application

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