ST STM32WL5x
Jump to navigation
Jump to search
The ST STM32WL5x are Cortex-M4 based microcontrollers. Some devices of this family feature a secondary Cortex-M0 core.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256 KB | 
|
| System memory | 0x1FFF0000 | 28 KB | 
|
| OTP area | 0x1FFF7000 | 1 KB |
|
| Option Bytes | 0x1FFF7800 | 128 B |
|
Watchdog Handling
- The device has a watchdog WWDG.
- The watchdog is fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
Some devices from this family feature a secondary Cortex-M0 core.
| Core | J-Link Support |
|---|---|
| Cortex-M4 |
|
| Cortex-M0 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core (Cortex-M4)
Init/Setup
- Enables debugging
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Secondary core (Cortex-M0)
Some devices feature a second Cortex-M0 core. J-Link software supports debugging on those cores. Flash programming support is only supported for Cortex-M4.
Init/Setup
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Evaluation Boards
- ST NUCLEO-WL55JC2 evaluation board: ST NUCLEO-WL55JC2
Example Application
- ST NUCLEO-WL55JC2 example application: ST NUCLEO-WL55JC2 Hello World