ST STM32C5
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The ST STM32C5 series are Cortex-M33® based wireless MCUs.
Flash Banks
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 1 MB [1] | 
|
| EDATA UserFlash | 0x08400000 | 64 KB [2] |
|
| EDATA DataFlash | 0x09000000 | 48 KB [2] |
|
EDATA
- The STM32C5 supports two different EDATA regions, only one of which can be active at a time.
- The active EDATA region is selected by the
EDATA_ENbit in theFLASH_OPTSRregister. - Enable the flash bank corresponding to the configured EDATA region:
EDATA_EN == 0→EDATA UserFlashis active at0x08400000.EDATA_EN == 1→EDATA DataFlashis active at0x09000000.
- For information on how to enable a flash bank, see: J-Link_Command_Strings#SetEnableFlashbank
Watchdog Handling
- The device has 2 watchdogs, IWDG & WWDG.
- Both are fed during flash programming.
Security Product Lifecycle programming
Security Product Lifecycle programming is implemented in Device Provisioner utility: ST_STM32C5_Security_Product_Lifecycle.
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.