Renesas RX671
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The Renesas RX671 are microcontrollers from Renesas, which are based on the RXv3 architecture.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Internal data flash | 0x100000 | 
|
Default | 8 KB |
| Internal program flash | 0xFFE00000/0xFFE80000/0xFFF00000 |
|
Default | 1024/1536/2048 KB |
| Option setting flash | 0xFE7F5D00 |
|
Default | 128 B |
Watchdog Handling
- The device has 2 watchdogs: WDTA, IWDT
- The watchdogs are fed during flash programming
Device Specific Handling
Connect
- As part of the connect sequence, OFS1 is modified by J-Link to allow debugging via FINE interface. J-Link restores the OFS1 state on debug session close.
Supported debug interfaces
The following debug interfaces are supported for the RX671 series:
- JTAG
- FINE
Evaluation Boards
Tracing
- There is no trace support for this device series