RISC-V

RISC-V is an open source CPU specification. RISC-V is not a single CPU, it is merely a standard which RISC-V devices have to follow. RISC-V is maintained by the RISC-V foundation (https://riscv.org). All relevant documents are in the public domain. There are various different CPU cores defined. The word is not fixed, it can range from 32-bits to 128bits. In reality, most implementations are 32-bit (RV32) or 64-bit (RV64). RISC-V is an alternative to the ARM architecture, owned by ARM (http://www.arm.com). ARM cores are designed and licensed by ARM only. The licensees are bound by the restrictive license terms and usually pay significant license fees.

ISA Variants

Numerous ISA (Instruction Set Architecture) variants are defined by the specification. The most common ones are:

ISA Name	Explanation
RV32I	Basic 32-bit CPU with 32 general purpose registers, no multiply / divide instruction.
RV64I	Basic 64-bit CPU with 32 general purpose registers, no multiply / divide instruction.
RV128I	Basic 128-bit CPU with 32 general purpose registers, no multiply / divide instruction.
RV32E	Basic 32-bit "embedded" CPU with integer capabilities and 16 General purpose registers, no multiply / divide instruction.
RV32ICM	RV32I + Compressed instruction support + multiply / divide instructions.
RV32ECM	RV32E + Compressed instruction support + multiply / divide instructions.

So there are basically 2 variants, I and E. The I variant is the classical, standard variant with 32 registers, where the E-variant comes with only 16 registers.

RV32I, RV64I, RV128I

This is the standard variant with 32 registers.

RV32E

The embedded variant. In an effort to reduce the core size (silicon footprint) of the CPU, this has been created. Reducing the number of registers reduces cores size and power consumption by about 25% (acc. to spec). Everything is kept identical to RV32I, with the exception of the number of registers. The spec says:

RV32E uses the same instruction-set encoding as RV32I, except that only registers x0 – x15 are provided. Any future standard extensions will not make use of the instruction bits freed up by the reduced register-specifier fields and so these are available for custom extensions.

So the E variant reduces the size of the core, but it does not take advantage of the instruction bits freed up, so it does not allow the compiler to generate smaller code.

ISA extensions

There are various optional extensions, available in the Machine ISA Register misa (-> 3.1.1 of spec)

Bit	Character	Description
0	A	Atomic extensions
1	B	Bit manipulation extensions (tentative)
2	C	Compressed extension (More efficient encoding of instructions, reducing code size)
3	D	Double-precision floating-point extension
4	E	RV32E, "Embedded" base ISA (not an extension). Means 16 general purpose registers only, in contrast to the I-variant
5	F	Single-precision floating-point extension
6	G	Additional standard extensions
7	H	Hypervisor extension
8	I	Base "integer" ISA variant for 32-register cores RV32I, RV64I, RV128I. Not an extension. In contrast to the E-variant.
9	J	Dynamically Translated Languages extension (tentative)
10	K	Reserved
11	L	Decimal Floating-Point extension (tentative)
12	M	Integer Multiply/Divide extension
13	N	User-level interrupts supported
14	O	Reserved
15	P	Packed-SIMD extension (tentative)
16	Q	Quad-precision floating-point extension
17	R	Reserved
18	S	Supervisor mode implemented
19	T	Transactional Memory extension (tentative)
20	U	User mode implemented
21	V	Vector extension (tentative)
22	W	Reserved
23	X	Non-standard extensions present
24	Y	Reserved
25	Z	Reserved

Programmer's view

The RISC-V is very similar to MIPS processor, with different instruction encoding.

Registers

The standard I variant comes with 32 registers (x0 - x31), where register 0 (x0) is hardwired to 0. There is also a PC, which has the same size as the registers. There is no flag register, so no carry, zero or sign flag.

Available implementations

There are various implementations available from different sources. Some implementations can be freely used, others are commercial.

Vendors

• SiFive http://www.sifive.com
• Andes Technology http://www.andestech.com

Debug interface

There are different specification versions that silicon vendors have been used to design their chip implementation.

Version	Supported	Notice
0.11		Early draft version
0.13.2		Stable version
1.0		Official ratified version

Supported Interfaces

The official debug specification defines JTAG-DTM as its only debug transport module (DTM).

Besides JTAG, vendors have implemented access via SWD and the CoreSight Architecture. The RISC-V core is available behind an exposed DAP.

J-Link supports both interfaces with RISC-V since V0.13.2.

Supported Features

• CPU
  • Single hart selection
  • Software breakpoints
  • Run control: Run/Halt/Single-Step
• Trigger Module
  • Hardware Breakpoints (mcontrol, mcontrol6)
  • Hardware Data Breakpoints (See Limitations)
• Memory access
  • via System Bus Access (SBA)
  • via progbuf (CPU)
  • via abstract command

Limitations

There are some limitations to keep in mind when using the J-Link for debugging RISC-V cores.

• There might be incompatibilities with implementations using pre-releases of the V1.0 (e.g. 1.0.0-STABLE, 1.0.0-rc1)
• Trigger types itrigger,etrigger, tmexttrigger are not supported
• Halt/Resume groups are not supported
• Multiple debug modules (DM) are not supported
• Data breakpoints might not be fully functional depending on hardware configuration e.g. data matching not available

If you require support for some of the features listed above, please contact our support at support@segger.com.

References

• RISC-V Foundation: https://riscv.org
• RISC-V Technical Specifications: https://riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+Technical+Specifications