Target Interface JTAG
JTAG is the acronym for Joint Test Action Group. Within this document, "the JTAG standard" means compliance with IEEE standard 1149.1-2001. Initially designed to verify designs and PCBs following manufacture, the JTAG standard has developed and expanded over time to become a standard for defining CPU debug interfaces.
Test access port (TAP)
JTAG defines a TAP, which is a general-purpose port capable of providing access to many test support functions built into a component. It consists of a minimum of three input connections (TDI, TCK, and TMS) and one output connection (TDO). An optional fourth input connection (nTRST) provides for asynchronous test-logic initialization.
| Pin | Type | Explanation |
|---|---|---|
| TCK | Input | The test-clock input (TCK) provides the clock for the test logic. |
| TDI | Input | Serial test instructions and data are received by the test logic at test-data input (TDI). |
| TMS | Input | The signal received at test-mode select (TMS) is decoded by the TAP controller to control test operations. |
| TDO | Output | Test-data output (TDO) is the serial output for test instructions and data from the test logic. |
| nTRST | Input (optional) | The optional test-reset (nTRST) input provides for asynchronous initialization of the TAP controller. |
The TAP controller
The TAP controller is a synchronous finite-state machine that responds to changes at the TMS and TCK signals of the TAP and controls the sequence of operations for the circuitry. TAP controller-state diagram:
Data registers (DR-Scan path)
JTAG requires at least two data registers to be present: the bypass and the boundary-scan register. Other registers are allowed but are not obligatory.
Bypass-data register
A single-bit register that passes information from TDI to TDO.
Boundary-scan data register
A test-data register that allows testing of board interconnections, as well as access to component input and output when testing system logic, etc.
Instruction register (IR-Scan path)
The instruction register holds the current instruction, and its content is used by the TAP controller in order to decide what test to perform or what data register to access. It consist of at least two shift-register cells.
State descriptions
Reset
The test logic is disabled so that normal operation of the chip's logic can continue unhindered. Regardless of the state the TAP controller is currently in, it can change its state into a reset state if TMS is high for at least five clock cycles. As long as TMS is high, the TAP controller remains in a reset state.
Idle
Idle is a TAP controller state between scan (DR or IR) operations. Once entered, this state remains active as long as TMS is low.
DR-Scan
A temporary controller state. If TMS remains low, a scan sequence for the selected data registers is initiated.
IR-Scan
A temporary controller state. If TMS remains low, a scan sequence for the instruction register is initiated.
Capture-DR
Data may be loaded to the selected test-data registers in parallel.
Shift-DR
With each clock, the test-data register that is connected between TDI and TDO shifts data one stage toward the serial output.
Exit1-DR
A temporary controller state.
Pause-DR
Shifting of the test-data register between TDI and TDO is temporarily halted.
Exit2-DR
A temporary controller state that allows a user to either go back into the Shift-DR state or to go on to Update-DR.
Update-DR
Data contained in the currently selected data register is loaded into a latched parallel output (for registers that have such a latch). The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process.
Capture-IR
Instructions may be loaded in parallel into the instruction register.
Shift-IR
With each clock, the instruction register shifts the values in the instruction register towards TDO.
Exit1-IR
A temporary controller state.
Pause-IR
A holding state that temporarily halts instruction shifting.
Exit2-IR
A temporary controller state that allows a user to either go back into the Shift-IR state or to go on to Update-IR.
Update-IR
The values contained in the instruction register are loaded into a latched parallel output from the shift-register path. Once latched, this new instruction becomes the current one. The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting process.