User contributions for Matthias
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9 September 2025
- 11:4711:47, 9 September 2025 diff hist 0 ST STM32U5 →QSPI Flash current
- 11:4611:46, 9 September 2025 diff hist +51 ST STM32U5 →QSPI Flash
25 August 2025
18 August 2025
- 09:4209:42, 18 August 2025 diff hist −1 Nuvoton M48x No edit summary current
- 09:4209:42, 18 August 2025 diff hist −30 Nuvoton M48x →Flash Banks
15 August 2025
- 09:2709:27, 15 August 2025 diff hist 0 J-Link Commander →Syntax current
11 August 2025
- 17:5617:56, 11 August 2025 diff hist 0 Renesas RA4L1 →Watchdog Handling current
- 17:5517:55, 11 August 2025 diff hist +4 Renesas RA4L1 →Flash Banks
- 17:5117:51, 11 August 2025 diff hist +187 Renesas RA4L1 →Flash Banks
7 August 2025
- 09:5409:54, 7 August 2025 diff hist +2 Nations N32H48x →Watchdog Handling current
6 August 2025
- 16:0316:03, 6 August 2025 diff hist +426 AlifSemi B1 No edit summary current
- 16:0316:03, 6 August 2025 diff hist +426 AlifSemi E1C No edit summary current
- 15:4615:46, 6 August 2025 diff hist −199 AlifSemi E1C No edit summary
- 15:4615:46, 6 August 2025 diff hist −199 AlifSemi B1 No edit summary
5 August 2025
- 10:1510:15, 5 August 2025 diff hist −1 ST STM32WB →RSS / FUS current
30 July 2025
- 11:0211:02, 30 July 2025 diff hist +69 J-Trace PRO Cortex →Supported cores current
- 11:0111:01, 30 July 2025 diff hist +66 J-Trace PRO Cortex-M →Supported cores current
- 11:0111:01, 30 July 2025 diff hist +75 J-Link EDU No edit summary
- 11:0011:00, 30 July 2025 diff hist +69 J-Link LITE Cortex-M →Supported cores current
- 10:5910:59, 30 July 2025 diff hist +67 J-Link LITE ARM →Supported cores current
28 July 2025
- 13:2213:22, 28 July 2025 diff hist +1 SEGGER Flash Loader →SEGGER_FL_GetFlashInfo current
23 July 2025
- 15:4415:44, 23 July 2025 diff hist +166 Microchip →Information on supported devices
- 15:4415:44, 23 July 2025 diff hist 0 N File:Microchip WBZ653 Curiosity TestProject ES V824.zip No edit summary current
- 15:3915:39, 23 July 2025 diff hist +1,190 N Microchip WBZ653 Curiosity Created page with "800px|thumb|right|Microchip WBZ653 Curiosity evaluation board This article describes specifics for the Microchip WBZ653 Curiosity evaluation board. It can be used to test & verify Microchip PIC32CX-BZ2 device support. __TOC__ == Minimum requirements == * J-Link software V7.96m or later == Preparing for J-Link == * Connect the J-Link to the debug header (J904). **RESET = NMCLR **VTref = TVDD **GND = GND **SWCLK = SWCLK **SWD..." current
- 15:3915:39, 23 July 2025 diff hist 0 N File:Microchip WBZ653 Curiosity connect.png No edit summary current
- 15:3315:33, 23 July 2025 diff hist +1,698 N Microchip PIC32CX BZ6 Created page with "__TOC__ The '''Microchip PIC32CX BZ6''' family is a general purpose, low-cost, Cortex-M4 microcontroller family of devices supporting multi-protocol wireless interfaces (Bluetooth and Zigbee). ==Flash Banks== ===Internal Flash=== {| class="seggertable" |- ! Device || Flash bank || Base address || Size || J-Link Support |- |- |rowspan="4"|PIC32CX2051BZ6 | Program flash || 0x01000000 || 2048 KB || style="text-align:center;"| {{YES}} |- | Boot flash || 0x00800000 || 64 KB..." current
- 13:4913:49, 23 July 2025 diff hist +290 Device Provisioner →Supported Devices and Features
- 13:4613:46, 23 July 2025 diff hist +19,136 N ST STM32WBA Option Bytes Programming Created page with "Category:Device Provisioner STM32WBA Option bytes programming and RDP locking/unlocking features are supported by Device Provisioner commandline tool. In order to use it, '''PCode_DevPro_ST_STM32WBA.pex''' script file must be specified as a commandline argument. __TOC__ == Important notes == # Performing RDP level 1 unlocking starts regression sequence. Flash memory is completely erased in this case. # Setting RDP to level 2 without OEM 2 p..." current
17 July 2025
- 16:3716:37, 17 July 2025 diff hist +388 ST STM32U5 →Evaluation Boards
16 July 2025
- 10:4810:48, 16 July 2025 diff hist +156 ESWIN EAM2011 →Flash Banks current
15 July 2025
- 13:0013:00, 15 July 2025 diff hist +7 J-Link RDI No edit summary current
11 July 2025
- 17:3617:36, 11 July 2025 diff hist −1 Nuvoton M25x No edit summary current
- 17:3617:36, 11 July 2025 diff hist −17 Nuvoton M25x No edit summary
- 17:3217:32, 11 July 2025 diff hist +6 Nuvoton M25x No edit summary
- 13:1313:13, 11 July 2025 diff hist +364 NXP i.MX RT1170 →Reset current
- 10:3910:39, 11 July 2025 diff hist +2 ESWIN EAM2011 →Flash Banks
- 10:3910:39, 11 July 2025 diff hist +15 ESWIN EAM2011 →Flash Banks
- 10:3910:39, 11 July 2025 diff hist +638 ESWIN EAM2011 →Flash Banks
10 July 2025
2 July 2025
- 08:3708:37, 2 July 2025 diff hist +569 Nordic Semiconductor nRF54Lxx No edit summary current
30 June 2025
- 16:3716:37, 30 June 2025 diff hist 0 Infineon CYT4DN No edit summary current
- 16:3716:37, 30 June 2025 diff hist +29 N Infineon CYT3DN Matthias moved page Infineon CYT3DN to Infineon CYT4DN current Tag: New redirect
- 16:3716:37, 30 June 2025 diff hist 0 m Infineon CYT4DN Matthias moved page Infineon CYT3DN to Infineon CYT4DN
- 16:3716:37, 30 June 2025 diff hist 0 Infineon →Information on supported devices
- 16:3316:33, 30 June 2025 diff hist +145 Infineon →Information on supported devices
- 16:3216:32, 30 June 2025 diff hist −1 Infineon CYT3DL →Flash memory layout current
- 16:3216:32, 30 June 2025 diff hist −1 Infineon CYT4DN →Flash memory layout
- 16:3216:32, 30 June 2025 diff hist +1,080 N Infineon CYT4DN Created page with "Category:Device families The Infineon '''CYT3DN''' is a subfamily of Infineon Traveo T2G microcontrollers containing two Cortex M7 and Cortex M0+ CPU. == SRAM == The CYT3DN family features 640 KB of SRAM located at 0x28000000. The first 2 KB are reserved for internal usage and may not be used. == Flash memory layout == The CYT3DLF series devices have 6336 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors and an area of..."
- 16:2216:22, 30 June 2025 diff hist +146 Infineon →Information on supported devices
- 16:2116:21, 30 June 2025 diff hist +1,093 N Infineon CYT3DL Created page with "Category:Device families The Infineon '''CYT3DL (TVII-C-2D-4M)''' is a subfamily of Infineon Traveo T2G microcontrollers containing a Cortex M7 and Cortex M0+ CPU. == SRAM == The CYT3DL family features 384 KB of SRAM located at 0x28000000. The first 2 KB are reserved for internal usage and may not be used. == Flash memory layout == The CYT3DLF series devices have 4160 KiB Code flash and a 128 KiB Work flash. Both flashes are split in an area of large sectors an..."