Renesas RA4C1: Difference between revisions
Jump to navigation
Jump to search
(Created page with "Category:Device families The '''Renesas RA4C1''' are energy-efficient microprocessors based on the Cortex-M33 core, well suited for cost-sensitive and low-power applications. __TOC__ ==Flash Banks== ===R7FA4C1BB=== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=Code flash | BaseAddress=0x0000_0000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=Default | Size=256 KB }} }} {{:Template:FlashBankTableRow |...") |
|||
| Line 43: | Line 43: | ||
==Evaluation Boards== | ==Evaluation Boards== | ||
*[[ | *[[Renesas_EK-RA4C1 | Renesas EK-RA4C1]] | ||
==Example Application== | ==Example Application== | ||
*[[Renesas_RA4C1_100pin_QFP_CPU_Evaluation_Board#Example_Project | Renesas RA4C1 100pin_QFP CPU Evaluation Board]] | *[[Renesas_RA4C1_100pin_QFP_CPU_Evaluation_Board#Example_Project | Renesas RA4C1 100pin_QFP CPU Evaluation Board]] | ||
Revision as of 10:45, 8 August 2025
The Renesas RA4C1 are energy-efficient microprocessors based on the Cortex-M33 core, well suited for cost-sensitive and low-power applications.
Flash Banks
R7FA4C1BB
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Code flash | 0x0000_0000 | 
|
Default | 256 KB |
| Option bytes | 0x0100_A100 |
|
Default | 512 B |
| Data Flash | 0x0800_0000 |
|
Default | 8 KB |
R7FA4C1BD
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Code flash | 0x0000_0000 |
|
Default | 512 KB |
| Option bytes | 0x0100_A100 |
|
Default | 512 B |
| Data Flash | 0x0800_0000 |
|
Default | 8 KB |
Watchdog Handling
- The device has two watchdogs WDT and IWDT.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Attach
Attach is supported.