Renesas RA4C1
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The Renesas RA4C1 are energy-efficient microprocessors based on the Cortex-M33 core, well suited for cost-sensitive and low-power applications.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Code Flash | 0x00000000 | 
|
Default | Up to 512 KB |
| Data Flash | 0x08000000 |
|
Default | 8 KB |
| Option Bytes | 0x0100A100 |
|
Default | 512 B |
| QSPI Flash [1] | 0x60000000 |
|
CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505 | up to 64MB |
| CLK@P104_nCS@P112_D0@P101_D1@P100_D2@P103_D3@P102 | up to 64MB | |||
| CLK@P204_nCS@P207_D0@P211_D1@P210_D2@P209_D3@P208 | up to 64MB | |||
- ↑
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for this Device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
Watchdog Handling
- The device has two watchdogs WDT and IWDT.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On connect it is checked if TrustZone is enabled.
The transfer type(S/NS) is adjusted from this setting.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Attach
Attach is supported.