Renesas RA4L1: Difference between revisions
(Created page with "Category:Device families The '''[SiliconVendor] [DeviceFamily]''' are [SHORT_DESCRIPTION] __TOC__ ==Flash Banks== ===Device Group1=== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=[Flash Bank 1] | BaseAddress=[Address] | JLinkSupport=yes | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=[Flash Loader 1] | Size=8 KB }} }} }} ===Device Group2=== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankNa...") |
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The ''' | The '''Renesas RA4L1''' are [SHORT_DESCRIPTION] | ||
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==Evaluation Boards== | ==Evaluation Boards== | ||
*[[ | *[[Renesas_EK-RA4L1 | Renesas EK-RA4L1]] | ||
==Example Application== | ==Example Application== | ||
*[[ | *[[Renesas_EK-RA4L1#Example_Project | Renesas EK-RA4L1]] | ||
Revision as of 12:25, 13 February 2025
The Renesas RA4L1 are [SHORT_DESCRIPTION]
Flash Banks
Device Group1
Flash Bank | Base address | J-Link Support | Loader | |
---|---|---|---|---|
Name | Size | |||
[Flash Bank 1] | [Address] | ![]() |
[Flash Loader 1] | 8 KB |
Device Group2
Flash Bank | Base address | J-Link Support | Loader | |
---|---|---|---|---|
Name | Size | |||
[Flash Bank 1] | [Address] | ![]() |
[Flash Loader 1] | 32 KB |
[Flash Bank 2] [1] | [Address] | ![]() |
[Flash Loader 1] | 32 KB |
[Flash Loader 2] | 16 KB |
- ↑
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for this Device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
ECC RAM [OPTIONAL]
- Describe ECC RAM restriction here.
Vector Table Remap [OPTIONAL]
- Describe Vector Table Remap here..
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
Core | J-Link Support |
---|---|
[CORE_NAME] | ![]() ![]() |
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
- The device uses Cortex-M Core reset, no special handling necessary, like described here.
- The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses Cortex-A reset, no special handling necessary, like described here.
- The device uses Cortex-R reset, no special handling necessary, like described here.
- The device uses ARMv8-A reset, no special handling necessary, like described here.
- The device uses ARMv8-R reset, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.