Renesas RA4L1: Difference between revisions

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{{:Template:FlashBankTable
{{:Template:FlashBankTable
| FlashBanks=
| FlashBanks=
{{:Template:FlashBankTableRow | BankName=Code Flash | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=Code flash | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=2 | Loader=
{{:Template:FlashLoader | Name=Default | Size=up to 512 KB}}
{{:Template:FlashLoader | Name='''Default''' | Size=Up to 512 KB }}
{{:Template:FlashLoader | Name=RAMLess | Size=Up to 512 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=Data Flash | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=Option bytes | BaseAddress=0x0100A100 | JLinkSupport=yes | NumOfLoaders=2 | Loader=
{{:Template:FlashLoader | Name=Default | Size=65 KB}}
{{:Template:FlashLoader | Name='''Default''' | Size=512 B }}
{{:Template:FlashLoader | Name=RAMLess | Size=512 B }}
}}
}}
{{:Template:FlashBankTableRow | BankName=Option Bytes | BaseAddress=0x0100A100| JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=Data Flash | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=2 | Loader=
{{:Template:FlashLoader | Name=Default | Size=512 B}}
{{:Template:FlashLoader | Name='''Default''' | Size=8 KB }}
{{:Template:FlashLoader | Name=RAMLess | Size=8 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=QSPI Flash <ref name="FootNote1" >
{{:Template:FlashBankTableRow | BankName=QSPI Flash <ref name="FootNote1" >
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}}
}}
<references />
<references />
==ECC RAM [OPTIONAL]==
*Describe ECC RAM restriction here.
==Vector Table Remap [OPTIONAL]==
*Describe Vector Table Remap here..


==Watchdog Handling==
==Watchdog Handling==
*The device does not have a watchdog.
*The device has two watchdogs WDT and IWDT.  
*The device has a watchdog [WATCHDOGNAME].
*If a watchdog is enabled, it is is fed during flash programming.
*The watchdog is fed during flash programming.
*If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
 
==Multi-Core Support [OPTIONAL]==
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
The [DeviceFamily]family comes with a variety of multi-core options.<br>
Some devices from this family feature a secondary core which is disabled after reset / by default.<br>
Some of the are available with enabled ''lockstep'' mode, only. <br>
{| class="seggertable"
|-
! Core || J-Link Support
|-
| [CORE_NAME] || style="text-align:center;"| {{YES}} / {{NO}}
|}
 
In below, the debug related multi-core behavior of the J-Link is described for each core:
===Main core===
====Init/Setup====
*Initializes the ECC RAM, see [[XXX | XXX]]
*Enables debugging
====Reset====
*Device specific reset is performed, see [[XXX | XXX]]
====Attach====
*Attach is not supported because the J-Link initializes certain RAM regions by default
===Secondary core(s)===
====Init/Setup====
*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
*If the secondary core is not enabled yet, it will be enabled / release from reset
====Reset====
No reset is performed.
====Attach====
*Attach is supported / desired


==Device Specific Handling==
==Device Specific Handling==
===Connect===
===Connect===
*On connect it is checked if TrustZone is enabled.<br> The transfer type(S/NS) is adjusted from this setting.
===Reset===
===Reset===
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
*The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]].
*The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]].
*The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]].
*The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]].
*The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]].
*The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]].
*The device uses custom reset:.....
==Limitations==
===Dual Core Support===
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
===Attach===
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
===Security===


==Evaluation Boards==
==Evaluation Boards==

Latest revision as of 17:56, 11 August 2025

The Renesas RA4L1 are Arm Cortex-M33 Based Low Power MCU with TrustZone, Segment LCD Controller and Advanced Security.

Flash Banks

Flash Bank Base address J-Link Support Loader
Name Size
Code flash 0x00000000 YES.png Default Up to 512 KB
RAMLess Up to 512 KB
Option bytes 0x0100A100 YES.png Default 512 B
RAMLess 512 B
Data Flash 0x08000000 YES.png Default 8 KB
RAMLess 8 KB
QSPI Flash [1] 0x60000000 YES.png CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505 up to 64MB
CLK@P104_nCS@P112_D0@P101_D1@P100_D2@P103_D3@P102 up to 64MB
CLK@P204_nCS@P207_D0@P211_D1@P210_D2@P209_D3@P208 up to 64MB
  1. ↑ QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
    J-Link supports multiple pin configurations for this Device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.

Watchdog Handling

  • The device has two watchdogs WDT and IWDT.
  • If a watchdog is enabled, it is is fed during flash programming.

Device Specific Handling

Connect

  • On connect it is checked if TrustZone is enabled.
    The transfer type(S/NS) is adjusted from this setting.

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

Example Application

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