Nordic Semiconductor nRF54Lxx: Difference between revisions

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(Created page with "Category:Device families The '''Nordic Semiconductor nRF54L''' are ultra low-power multiprotocol wireless System-on-Chip (SoC) supporting Bluetooth Low Energy, Bluetooth mesh, Thread, and Matter technologies. __TOC__ ==Flash Banks== ===nRF54L15=== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=Internal flash | Size=1524 KB}} }...")
 
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==Flash Banks==
==Flash Banks==
===nRF54LM20===
{{:Template:FlashBankTable
| FlashBanks=
{{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Internal flash | Size=2036 KB}}
}}
{{:Template:FlashBankTableRow | BankName=UICR | BaseAddress=0x00FFD000 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
{{:Template:FlashBankTableRow | BankName=OTP | BaseAddress=0x00FFD500 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
}}
===nRF54L15===
===nRF54L15===
{{:Template:FlashBankTable
{{:Template:FlashBankTable
Line 9: Line 23:
{{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Internal flash | Size=1524 KB}}
{{:Template:FlashLoader | Name=Internal flash | Size=1524 KB}}
}}
{{:Template:FlashBankTableRow | BankName=UICR | BaseAddress=0x00FFD000 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
{{:Template:FlashBankTableRow | BankName=OTP | BaseAddress=0x00FFD500 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
}}
===nRF54L10===
{{:Template:FlashBankTable
| FlashBanks=
{{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Internal flash | Size=1022 KB}}
}}
{{:Template:FlashBankTableRow | BankName=UICR | BaseAddress=0x00FFD000 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
{{:Template:FlashBankTableRow | BankName=OTP | BaseAddress=0x00FFD500 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=- | Size=-}}
}}
}}
===nRF54L05===
{{:Template:FlashBankTable
| FlashBanks=
{{:Template:FlashBankTableRow | BankName=RRAM | BaseAddress=0x00000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Internal flash | Size=500 KB}}
}}
}}
{{:Template:FlashBankTableRow | BankName=UICR | BaseAddress=0x00FFD000 | JLinkSupport=no | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=UICR | BaseAddress=0x00FFD000 | JLinkSupport=no | NumOfLoaders=1 | Loader=
Line 32: Line 74:
| Cortex-M33 || style="text-align:center;"| {{YES}}
| Cortex-M33 || style="text-align:center;"| {{YES}}
|-
|-
| RISC-V RV32 || style="text-align:center;"| {{NO}}
| RISC-V RV32 || style="text-align:center;"| {{YES}}
|}
|}


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===Reset===
===Reset===
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
===RISC-V core===
====Attach====
*Attach is supported.
==Device Specific Handling==
===Reset===
*The device uses normal RISC-V reset, no special handling necessary, like described [[J-Link_Reset_Strategies | here]].


==Limitations==
==Limitations==
===Dual Core Support===
===RISC-V security attributes===
The nRF54Lxx devices feature a second RISC-V core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
After device start-up, RAM and RRAM memory regions are treated as secure. To allow RISC-V core execute from these regions, the core is configured as secure peripheral.
 
===Security===
===Security===
The nRF54Lxx Series uses special debug locking mechanism. To gain access to debugging features the following steps should be performed: 1) UICR registers should be configured to enable debug port. 2) User application should set corresponding registers to open access to debug port.
The nRF54Lxx Series uses special debug locking mechanism. To gain access to debugging features the following steps should be performed: 1) UICR registers should be configured to enable debug port. 2) User application should set corresponding registers to open access to debug port.

Latest revision as of 08:37, 2 July 2025

The Nordic Semiconductor nRF54L are ultra low-power multiprotocol wireless System-on-Chip (SoC) supporting Bluetooth Low Energy, Bluetooth mesh, Thread, and Matter technologies.

Flash Banks

nRF54LM20

Flash Bank Base address J-Link Support Loader
Name Size
RRAM 0x00000000 YES.png Internal flash 2036 KB
UICR 0x00FFD000 NO.png - -
OTP 0x00FFD500 NO.png - -


nRF54L15

Flash Bank Base address J-Link Support Loader
Name Size
RRAM 0x00000000 YES.png Internal flash 1524 KB
UICR 0x00FFD000 NO.png - -
OTP 0x00FFD500 NO.png - -


nRF54L10

Flash Bank Base address J-Link Support Loader
Name Size
RRAM 0x00000000 YES.png Internal flash 1022 KB
UICR 0x00FFD000 NO.png - -
OTP 0x00FFD500 NO.png - -


nRF54L05

Flash Bank Base address J-Link Support Loader
Name Size
RRAM 0x00000000 YES.png Internal flash 500 KB
UICR 0x00FFD000 NO.png - -
OTP 0x00FFD500 NO.png - -


Watchdog Handling

  • The device has two watchdogs WDT30 and WDT31.
  • The watchdogs are fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The nRF54Lxx family comes with a variety of multi-core options.

Core J-Link Support
Cortex-M33 YES.png
RISC-V RV32 YES.png

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Attach

  • Attach is supported.

Device Specific Handling

Reset

  • The device uses normal Cortex-M reset, no special handling necessary, like described here.

RISC-V core

Attach

  • Attach is supported.

Device Specific Handling

Reset

  • The device uses normal RISC-V reset, no special handling necessary, like described here.

Limitations

RISC-V security attributes

After device start-up, RAM and RRAM memory regions are treated as secure. To allow RISC-V core execute from these regions, the core is configured as secure peripheral.

Security

The nRF54Lxx Series uses special debug locking mechanism. To gain access to debugging features the following steps should be performed: 1) UICR registers should be configured to enable debug port. 2) User application should set corresponding registers to open access to debug port. Optionally J-Link can perform a full chip erase, to temporarily reopen debug access until next power reset.

Evaluation Boards

Example Application

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