Renesas RA4L1

The Renesas RA4L1 are Arm Cortex-M33 Based Low Power MCU with TrustZone, Segment LCD Controller and Advanced Security.

Flash Banks

Device Group1

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Data Flash	0x08000000		default	8 KB

Device Group2

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Code Flash	0x00000000		default	32 KB
Data Flash	0x08000000		default	32 KB
Option Bytes	0x0100A100		default	32 KB
QSPI Flash	0x60000000		CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505	up to 64MB
			CLK@P104_nCS@P112_D0@P101_D1@P100_D2@P103_D3@P102	up to 64MB
			CLK@P204_nCS@P207_D0@P211_D1@P210_D2@P209_D3@P208	up to 64MB

ECC RAM [OPTIONAL]

• Describe ECC RAM restriction here.

Vector Table Remap [OPTIONAL]

• Describe Vector Table Remap here..

Watchdog Handling

• The device does not have a watchdog.
• The device has a watchdog [WATCHDOGNAME].
• The watchdog is fed during flash programming.
• If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.

Multi-Core Support [OPTIONAL]

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.

Core	J-Link Support
[CORE_NAME]	/

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

• Initializes the ECC RAM, see XXX
• Enables debugging

Reset

• Device specific reset is performed, see XXX

Attach

• Attach is not supported because the J-Link initializes certain RAM regions by default

Secondary core(s)

Init/Setup

• If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
• If the secondary core is not enabled yet, it will be enabled / release from reset

Reset

No reset is performed.

Attach

• Attach is supported / desired

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.
• The device uses Cortex-M Core reset, no special handling necessary, like described here.
• The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
• The device uses Cortex-A reset, no special handling necessary, like described here.
• The device uses Cortex-R reset, no special handling necessary, like described here.
• The device uses ARMv8-A reset, no special handling necessary, like described here.
• The device uses ARMv8-R reset, no special handling necessary, like described here.
• The device uses custom reset:.....

Limitations

Dual Core Support

Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.

Attach

Attach is not supported by default because the J-Link initializes certain RAM regions by default.

Evaluation Boards

• Renesas EK-RA4L1

Example Application

• Renesas EK-RA4L1