TI AWR2944
The TI AWR294x series devices are SoCs with multiple processors. This includes an dual-core(lockstep) Arm® Cortex®-R5F, an Arm® Cortex®-M4F(HSM) and Digital Signal Processing (C66x) processor.
Flash Banks
AWR2944
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| External QSPI Flash | 0xC6000000 | 
|
Default | Up to 32MB |
Watchdog Handling
- The device has multiple watchdogs.
- If the watchdogs are active they are fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The AWR294x device family comes with a variety of multi-core options.
The Cortex-R5 cores are only supported in lockstep configuration mode.
AWR2944
| Core | J-Link Support |
|---|---|
| MSS_R5_0 MSS_R5_1(lockstep) |
|
| DSS_C66x | 
|
| RSS_CR4 |
|
| MSS_M4 (HSM) |
|
Device Specific Handling
Bootloader process
The unique Bootloader process of the device causes issues if the primary bootloader (RBL) can not find a user bootloader (SBL)
in the external flash during boot.
In this case the HSM core will cause a device reset after roughly 3 minutes, which will make flash programming and debugging not possible.
Therefore, for the best experience it should be ensured that a user bootloader is programmed into flash.
Otherwise only a Power-on-reset of the device will allow correct programming and debugging, albeit only for a few minutes.
Connect
- On connect a reset of the device is executed, this is necessarry to guarantee a normal working condition of the cpu.
Reset
- The device uses custom reset:
- The device is reset using the SoCs main control registers