TI AM261x

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The TI AM261x are microcontrollers based on Cortex-R5 cores.

Supported devices

Refer to the supported device list for a full list of all supported AM261x family devices, their corresponding names and connection diagrams.

Target interfaces

Interface J-Link support Flasher support
JTAG YES.png YES.png |-
SWD YES.png YES.png |-

Flash Banks

Flash bank Base address J-Link support Flasher support Loader
Name Bank size
QSPI Flash 0x60000000 YES.png YES.png Default 128 MB


QSPI flash

The QSPI flashloader uses the following pin configuration:

Alternate function Port / Pin
OSPI0_CLK GPIO2
OSPI0_NCS0 GPIO0
OSPI0_IO0 GPIO3
OSPI0_IO1 GPIO4
OSPI0_IO2 GPIO5
OSPI0_IO3 GPIO6
OSPI0_RES0 GPIO66

RAM

  • If the DevBoot mode is selected, TCMA RAM and L2 OCRAM will be initialized for correct ECC operation during the connect phase.

Watchdog Handling

  • The device has two watchdogs: WWDT0 and WWDT1: one for each core.
  • During flash programming the only WWDT0(core 0) is fed, as the core should not access the watchdog of another core.

Device specific handling

Reset

  • The device reset is not performed, as it requires multi-core and boot-loader handling.

Attach

Attach is a debugging feature which exclusively applies to J-Link and J-Trace and does not apply to Flasher.

  • Attach is not supported when the device is in the DevBoot mode and TCMA RAM is used(ECC initialization is performed).

Security

Multi-core support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The AM261x family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which function as a diagnostic core(Lockstep mode) by default.
When connecting to a secondary core, it will be switched to the Dual-core mode.

Core J-Link Support
Arm Cortex-R5F_0 YES.png
Arm Cortex-R5F_1 YES.png

Below the debug related multi-core behavior of the J-Link is described for each core:

R5_0 (Main core)

Init/Setup

  • Initializes the ECC TCMA RAM and L2 OCRAM only in DevBoot mode.

Reset

  • A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
    If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
    If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.

Attach

  • Attach is not supported when the device is in the DevBoot mode and TCMA RAM or L2 OCRAM is used (ECC initialization is performed).

R5_1 (Secondary core)

Init/Setup

  • Initializes the ECC TCMA RAM only in DevBoot mode.

Reset

No reset is performed.

  • A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
    If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
    If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.

Attach

  • Attach is not supported when the device is in the DevBoot mode and TCMA RAM L2 OCRAM is used (ECC initialization is performed).

Multicore Example Project

The following example project demonstrates a multicore debugging setup using two Ozone instances, based on two FreeRTOS instances running on R5_0 and R5_1 respectively. The project runs out of the box on TI AM261x SOM. For more information, please read the provided README.md file.

Note: The example is shipped with a compiled .JLinkScriptfile and without source files. Should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

Note: Currently, it is possible for the custom Ozone toolbar with multicore control buttons to not be visible by default when Ozone is not in full-screen mode. Should this be the case, simply disable and re-enable the custom toolbar by toggling it on and off in View → Toolbars → Custom.

Limitations

  • QSPI/OSPI programming in all boot modes except DevBoot is limited to three minutes because the watchdog timer is active and can only be handled or disabled after the second boot stage has completed successfully.

Evaluation Boards

Example Application