Silergy SA32D
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The Silergy SA32D series are Automotive RISC-V based microcontrollers.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support | Loaders |
|---|---|---|---|---|
| Code Flash | 0x10000000 | 2048 KB |  |
Default |
| Code Flash | 0x10200000 | 2048 KB | |
Default |
| Code Flash | 0x10400000 | 2048 KB | |
Default |
| Code Flash | 0x10600000 | 2048 KB | |
Default |
| Code Flash | 0x10800000 | 2048 KB | |
Default |
| Data Flash 0 (Non-cached) | 0x11000000 | 128 KB | |
Default |
| Data Flash 0 (Cached) | 0x11020000 | 128 KB | |
Default |
| Data Flash 1 (Cached) | 0x11040000 | 128 KB | |
Default |
| Data Flash 1 (Non-cached) | 0x11060000 | 128 KB | |
Default |
| Data Flash 2 | 0x13000000 | 128 KB | |
Default |
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SA32D series has up to five cores that can operate indipendently of each other.
| Core | J-Link Support |
|---|---|
| 5 x RISC-V |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core 0
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.
Attach
- Attach is supported.
Secondary cores 1-4
Connect
- On connect the device is configured for Multi-core boot.
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.
Attach
- Attach is supported.
Connect
- Lockstep mode is disabled.
- The reset vector is set to a debug loop at the start of SRAM2.
- The core is released from reset.
Watchdog Handling
- The device has a SWWDG and EWDG. They are refreshed during flash programming when necessary.