ST STM32MP21x
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The ST STM32MP21 are the second generation of STM32 application processors offering higher performances with a 64-bit platform, specifically designed for industrial applications. It includes 1x Cortex-A35 and 1x Cortex-M33 cores.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The STM32MP21 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| ARM Cortex-A35 | 
|
| ARM Cortex-M33 |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
ARM Cortex-A35 core
Init/Setup
- If it is the main boot core, it is responsible for enabling debugging access.
Reset
- Reset is not implemented, as device uses bootloader and can restrict access to system resources.
- If security resource isolation is used, reset may not be generated, but instead synchronos abort event.
Attach
- Attach is supported.
ARM Cortex-M33 core
Init/Setup
- If it is the main boot core, is responsible for enabling debugging access.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Attach
- Attach is supported.