ST STM32G5
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The ST STM32G5 are Cortex-M33 based MCUs.
Supported devices
Refer to the supported device list for a full list of all supported STM32G5 family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG |  |
|
| SWD | |
|
Flash Banks
Internal Flash
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Non-secure Internal flash | 0x08000000 | |
|
Default | Up to 512 KB |
| Secure Internal flash | 0x0C000000 |  |
|
Default | Up to 512 KB |
ECC Flash
The flash is ECC protected. When programming code with J-Link, the device flash controller automatically programs the correct ECC values. A 9-bit ECC complements each 128-bit data flash memory word.
Watchdog Handling
- The device has a window watchdog (WWDG) and an independent watchdog (IWDG).
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
- For STM32G5 devices, connect under reset is supported.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Option bytes programming and life-cycle management
- Option bytes programming on STM32G5 series of devices and life-cycle management are supported via dedicated utility Device Provisioner. It supports the following features: option bytes programming, product state change, provisioning of keys required for debug authentication, device authentication with certificate or password, device regression(unlock and full-chip erase). More details about STM32G5 option bytes programming, life-cycle management and provisioning please refer to: STM32G5 Security Product Lifecycle.