ST SR6P7
The ST SR6P7 are Stellar P series microcontrollers, which include six Arm Cortex-R52+ cores and three Arm Cortex-M4 cores.
Supported devices
Refer to the supported device list for a full list of all supported SR6P7 family devices, their corresponding names and connection diagrams.
Supported device revisions
| Revision | J-Link Support |
|---|---|
| Cut 1.0 | 
|
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG | |
|
| SWD | |
|
Flash banks
The following flash banks can be programmed via Cortex-R52 Cluster 0 Core 0:
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| RWW Partition 0 | 0x28000000 | |
|
Default | 1792 KB |
| RWW Partition 1 | 0x281C0000 | |
|
Default | 2048 KB |
| RWW Partition 2 | 0x28400000 | |
|
Default | 1792 KB |
| RWW Partition 3 | 0x285C0000 | |
|
Default | 2048 KB |
| RWW Partition 4 | 0x28800000 | |
|
Default | 2048 KB |
| RWW Partition 5 | 0x28A00000 | |
|
Default | 2048 KB |
| RWW Partition 6 | 0x28C00000 | |
|
Default | 2048 KB |
| RWW Partition 7 | 0x28E00000 | |
|
Default | 2048 KB |
| RWW Partition 8 | 0x29000000 | |
|
Default | 2048 KB |
| RWW Partition 9 | 0x29400000 | |
|
Default | 2048 KB |
| EEPROM / RWW 10 | 0x29E00000 | |
|
Default | 512 KB |
| UTEST / RWW 1 | 0x29F80000 | |
|
Default | 32 KB |
| Boot Code Sector / RWW 1 | 0x29FB8000 |  |
|
- | - |
Flasher stand-alone mode is not supported yet.
HSM flash banks
The following flash banks can be programmed via the HSM core:
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| HSM Code A / RWW 11 | 0x00000000 | |
|
Default | 512 KB |
| HSM Code B / RWW 12 | 0x00100000 | |
|
Default | 512 KB |
| HSM Data / RWW 13 | 0x003A0000 | |
|
Default | 128 KB |
| HSM UT / RWW 13 | 0x0037C000 | |
|
Default | 16 KB |
Flasher standalone mode is not supported yet.
Flash programming
- Single-ended mode is not supported.
- The flash controller does not provide an explicit erase function.
- An explicit erase operation is therefore not required before reprogramming the flash. Previously programmed flash can be reprogrammed directly.
- If the clock registers are in their reset state, the clock is initialized to achieve a higher programming speed.
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual. ECC RAM initialization is done for Cluster 0 Core 0, see below.
Multi-Core Support
| Core | J-Link Support |
|---|---|
| Cluster 0 Core 0 |
|
| Cluster 0 Core 1 |
|
| Cluster 1 Core 0 |
|
| Cluster 1 Core 1 |
|
| Cluster 2 Core 0 |
|
| Cluster 2 Core 1 |
|
| DSPH |
|
| DME |
|
| HSM |
|
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6P7 family comes with 6 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled split lock mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cluster 0 Core 0 Cortex-R52
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
Reset
- ARMv8-R Reset is performed like described here.
- Initializes 256KB ECC RAM starting at 0x60000000
- WDT is enabled by default. If it is enabled, it will be disabled.
Attach
- Attach is supported if WorkRAM init is skipped.
Cluster 0 Core 1 Cortex-R52
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 1 Core 0 Cortex-R52
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 1 Core 1 Cortex-R52
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 2 Core 0 Cortex-R52
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 2 Core 1 Cortex-R52 (if available)
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
- To connect to this core, bit split_lock has to be set to 1 on DCF Global_CONF.
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
DSPH Core Cortex-M4
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
DME Core Cortex-M4
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
HSM Core
Init/Setup
- Initializes 64KB ECC RAM starting at 0x00800000
- SWT is enabled by default. If it is enabled, it will be disabled.
Reset
- Functional reset is executed.
Attach
- Attach is supported if WorkRAM init is skipped.
Device Specific Handling
Reset
- Depending on connected core, different resets are performed, see above.