ST SR6P6

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The ST SR6P6 are Stellar P series microcontrollers, which include six Arm Cortex-R52+ cores and three Arm Cortex-M4 cores.

Supported devices

Refer to the supported device list for a full list of all supported SR6P6 family devices, their corresponding names and connection diagrams.

Supported device revisions

Revision J-Link Support
Cut 1.0
Cut 1.1
Cut 1.2

Target interfaces

Interface J-Link support Flasher support
JTAG
SWD

Flash banks

The following flash banks can be programmed via Cortex-R52 Cluster 0 Core 0:


Flash bank Base address J-Link support Flasher support Loader
Name Bank size
RWW Partition 0 0x28000000 Default 1792 KB
RWW Partition 1 0x281C0000 Default 2048 KB
RWW Partition 2 0x28400000 Default 1792 KB
RWW Partition 3 0x285C0000 Default 2048 KB
RWW Partition 4 0x28800000 Default 2048 KB
RWW Partition 5 0x28C00000 Default 2048 KB
RWW Partition 6 0x29000000 Default 2048 KB
RWW Partition 7 0x29400000 Default 2048 KB
EEPROM / RWW 8 0x29E00000 Default 512 KB
UTEST / RWW 1 0x29F80000 Default 32 KB
Boot Code Sector / RWW 1 0x29FB8000 - -


Note:
Flasher stand-alone mode is not supported yet.

HSM flash banks

The following flash banks can be programmed via the HSM core:


Flash bank Base address J-Link support Flasher support Loader
Name Bank size
HSM Code A / RWW 9 0x00000000 Default 256 KB
HSM Code B / RWW 10 0x00100000 Default 256 KB
HSM Data / RWW 11> 0x003A0000 Default 128 KB
HSM UT / RWW 11 0x0037C000 Default 16 KB


Note:
Flasher standalone mode is not supported yet.

Flash programming

  • Single-ended mode is not supported.
  • The flash controller does not provide an explicit erase function.
  • An explicit erase operation is therefore not required before reprogramming the flash. Previously programmed flash can be reprogrammed directly.
  • If the clock registers are in their reset state, the clock is initialized to achieve a higher programming speed.

ECC Flash

Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.

ECC RAM

Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual. ECC RAM initialization is done for Cluster 0 Core 0, see below.

Multi-Core Support

Core J-Link Support
Cluster 0 Core 0
Cluster 0 Core 1
Cluster 1 Core 0
Cluster 1 Core 1
Cluster 2 Core 0
Cluster 2 Core 1
DSPH
DME
HSM

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6P6 family comes with 6 Cortex-R52 and 3 Cortex-M4 cores. Some of them are available with enabled split lock mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:

Cluster 0 Core 0 Cortex-R52

Init/Setup

  • WDT is enabled by default. If it is enabled, it will be disabled.

Reset

  • ARMv8-R Reset is performed like described here.
  • Initializes 256KB ECC RAM starting at 0x60000000
  • WDT is enabled by default. If it is enabled, it will be disabled.

Attach

  • Attach is supported if WorkRAM init is skipped.

Cluster 0 Core 1 Cortex-R52

Init/Setup

  • WDT is enabled by default. If it is enabled, it will be disabled.
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cluster 1 Core 0 Cortex-R52

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cluster 1 Core 1 Cortex-R52

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cluster 2 Core 0 Cortex-R52

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

Cluster 2 Core 1 Cortex-R52 (if available)

Init/Setup

  • WDT is disabled
  • If core is not enabled, it will be enabled (set to DRUN condition).
  • To connect to this core, bit split_lock has to be set to 1 on DCF Global_CONF.

Reset

  • ARMv8-R Reset is performed like described here.

Attach

  • Attach is supported

DSPH Core Cortex-M4

Init/Setup

  • none

Reset

  • Cortex-M Typ 0 normal reset is performed like described here.

Attach

  • Attach is supported

DME Core Cortex-M4

Init/Setup

  • none

Reset

  • Cortex-M Typ 0 normal reset is performed like described here.

Attach

  • Attach is supported

HSM Core

Init/Setup

  • Initializes 64KB ECC RAM starting at 0x00800000
  • SWT is enabled by default. If it is enabled, it will be disabled.

Reset

  • Functional reset is executed.

Attach

  • Attach is supported if WorkRAM init is skipped.

Device Specific Handling

Reset

  • Depending on connected core, different resets are performed, see above.

Debug Authentication

Authentication via JTAG passwords is supported by J-Link and will be executed on connect if necessary.
A destructive reset may reset the passwords and authentication may have to be done again.
The JTAG passwords become active when lifecycle, passwords and necessary DCFs are set correctly.
Please refer to the security reference manual.

Specifying the JTAG passwords using J-Link Command String

This is the recommended method as the specified JTAG passwords will be used for the whole session. This way, the keys may not specified multiple times (e.g. if a reset is performed).
The J-Link Command String SetCPUConnectIDCode <Key> needs to be passed to the J-Link DLL before establishing the target connection(see example below). Up to two Passwords can be specified via this way, JTAG password for external tool and JTAG password for external tool for HSM. If both passwords are used, they have to be applied in one IDCODE string, which first contains the JTAG password for external tool and then following the JTAG password for external tool for HSM. It is not possible to specify only the JTAG password for external tool for HSM, because the JTAG password for external tool may be needed, too.

Example JTAG password for external tool:

  • Password0: 0x01234567
  • Password1: 0x89ABCDEF
  • Password2: 0x00224466
  • Password3: 0x88AABBCC
  • Password4: 0x11335577
  • Password5: 0x99DDEEFF
  • Password6: 0xA0B1A3B3
  • Password7: 0x4D5E6E7D

Example JTAG password for external tool for HSM:

  • Password0: 0xF8E7E6F5
  • Password1: 0x4E3F2F1E
  • Password2: 0xD8D7C6C5
  • Password3: 0x4C3C2D1D
  • Password4: 0xB8A7A6B5
  • Password5: 0x1A3B2B1A
  • Password6: 0x08070605
  • Password7: 0x40302010

To unlock the main cores: 

 exec SetCPUConnectIDCODE 67452301EFCDAB8966442200CCBBAA8877553311FFEEDD99B3A3B1A07D6E5E4D

To unlock the HSM core: 

 exec SetCPUConnectIDCODE 67452301EFCDAB8966442200CCBBAA8877553311FFEEDD99B3A3B1A07D6E5E4DF5E6E7F81E2F3F4EC5C6D7D81D2D3C4CB5A6A7B81A2B3B1A0506070810203040

Specifying the authentication code using the ID Code dialog

This feature will be available soon.

Specifying the JTAG password via J-Link script file

The JTAG password can be specified via J-Link script file as follows:
To unlock the main cores: 

  JLINK_ExecCommand("SetCPUConnectIDCODE = 67452301EFCDAB8966442200CCBBAA8877553311FFEEDD99B3A3B1A07D6E5E4D");

To unlock the HSM core: 

  JLINK_ExecCommand("SetCPUConnectIDCODE = 67452301EFCDAB8966442200CCBBAA8877553311FFEEDD99B3A3B1A07D6E5E4DF5E6E7F81E2F3F4EC5C6D7D81D2D3C4CB5A6A7B81A2B3B1A0506070810203040");

Because the SR6P6 device already uses InitTarget() and ConfigTargetSettings(), this can only be done via a modified ConfigTargetSettings() function.
Please get in touch with the SEGGER support about the ConfigTargetSettings() for the SR6P6.

Evaluation Boards

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