ST SR6G3
The ST SR6G3xx are Stellar G series microcontroler, which include 4 Cortex-R52+ and 2 Cortex-M4.
Supported devices
Refer to the supported device list for a full list of all supported SR6G3 family devices, their corresponding names and connection diagrams.
Supported device revisions
| Revision | J-Link Support |
|---|---|
| Cut 1.0 | 
|
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG | |
|
| SWD | |
|
Flash banks
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| RWW Partition 0[1] | 0x28000000 | |
|
default | 3840 KB |
| RWW Partition 1[1] | 0x28400000 | |
|
default | 3840 KB |
| EEPROM / RWW 2[1] | 0x29E00000 | |
|
default | 128 KB |
| UTEST / RWW 0[1] | 0x29F80000 | |
|
default | 32 KB |
| Boot Code Sector / RWW 0 | 0x29FB8000 | |
|
default | 16 KB |
| HSM Code A / RWW 3[2] | 0x00000000 | |
|
default | 512 KB |
| HSM Code B / RWW 3[2] | 0x00080000 | |
|
default | 512 KB |
| HSM Data / RWW 3[2] | 0x003A0000 | |
|
default | 128 KB |
| HSM UT / RWW 3[2] | 0x0037C000 | |
|
default | 16 KB |
Flash programming
Single ended mode is not supported.
The flash controller has no explicit erase function.
When reprogramming flash an explicit erase before programming is not necessary. Already programmed flash can be directly reprogrammed.
ECC Flash
Device has ECC Flash, but no special init necessary. Please refer to the reference Manual.
ECC RAM
Device has ECC RAM, init before first use is necessary. Please refer to the reference Manual. ECC RAM initialization is done for Cluster 0 Core 0, see below.
Multi-Core Support
| Core | J-Link Support |
|---|---|
| Cluster 0 Core 0 |
|
| Cluster 0 Core 1 |
|
| Cluster 0 Core 2 |
|
| Cluster 0 Core 3 |
|
| DSPH |
|
| HSM |
|
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The SR6G3 family comes with 4 Cortex-R52 and 2 Cortex-M4 cores. Some of them are available with enabled split lock mode, only.
Please refer to the reference manual.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cluster 0 Core 0 Cortex-R52
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
Reset
- ARMv8-R Reset is performed like described here.
- Initializes 256KB ECC RAM starting at 0x60000000
- WDT is enabled by default. If it is enabled, it will be disabled.
Attach
- Attach is not supported, because of ECC RAM initialization.
- Attach can be done by selecting Cortex-R52 as target device with the restriction that flash breakpoints are not available.
Cluster 0 Core 1 Cortex-R52
Init/Setup
- WDT is enabled by default. If it is enabled, it will be disabled.
- If core is not enabled, it will be enabled (set to DRUN condition).
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 0 Core 2 Cortex-R52 (if available)
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
- To connect to this core, bit split_lock has to be set to 1 on DCF Global_CONF.
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
Cluster 0 Core 3 Cortex-R52 (if available)
Init/Setup
- WDT is disabled
- If core is not enabled, it will be enabled (set to DRUN condition).
- To connect to this core, bit split_lock has to be set to 1 on DCF Global_CONF.
Reset
- ARMv8-R Reset is performed like described here.
Attach
- Attach is supported
DSPH Core Cortex-M4
Init/Setup
- none
Reset
- Cortex-M Typ 0 normal reset is performed like described here.
Attach
- Attach is supported
HSM Core
Init/Setup
- Initializes 64KB ECC RAM starting at 0x00800000
- SWT is enabled by default. If it is enabled, it will be disabled.
Reset
- Functional reset is executed.
Attach
- Attach is supported if WorkRAM init is skipped.
Device Specific Handling
Reset
- Depending on connected core, different resets are performed, see above.