ST LIS331EB

The ST LIS331EB are accelerometers based on the ARM Cortex-M0 core.

Flash Banks

Flash Bank	Base address	Size	J-Link Support
Internal Flash	0x10010000	64KB

Watchdog Handling

The device has a watchdog that is not fed during flash programming.

Device Specific Handling

Connect

• The device has ECC RAM that is initialized first.
• Protection level is checked during connect. If the device is secured, J-Link will ask the user for permission to mass erase the device.

Reset

The device uses a custom reset: The BootROM runs first after reset and the core is halted afterwards.

Evaluation Boards

• LIS331EB Discovery

Example Application

• LIS331EB Discovery Hello World