Renesas RZ/A1L
Jump to navigation
Jump to search
The Renesas RZ/A1L is are high-end 32-bit CPUs based on the Cortex-A9 core.
Flash Banks
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| External QSPI flash | 0x18000000 | Up to 64MB | 
|
There is a second device name for each device that uses Parallel Mode to access two SPI flashes in parallel. QSPI Flash programming support is provided through the following pin configs:
Quad-SPI Interface Pins
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 0 for single SPI:
| Alternate function | Port / Pin |
|---|---|
| SPBCLK_0 | P4_4 |
| SPBSSL_0 | P4_5 |
| SPIO00 | P4_6 |
| SPIO10 | P4_7 |
| SPIO20 | P4_2 |
| SPIO30 | P4_3 |
For the Renesas RZ A1L series device the following port pins are used to interface the (Q)SPI flash at channel 1 are for dual SPI:
| Alternate function | Port / Pin |
|---|---|
| SPIO01 | P3_10 |
| SPIO11 | P3_11 |
| SPIO21 | P3_12 |
| SPIO31 | P3_13 |
Watchdog Handling
The device has a watchdog that turned off during flash programming and turned back on afterwards if enabled.
Device specific handling
Reset
The device uses Cortex-A reset, no special handling necessary, like described here.