Renesas RX660
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The Renesas RX660 are microcontrollers from Renesas, which are based on the RXv3 architecture.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Internal data flash | 0x00100000 | 
|
Default | 32 KB |
| Option setting flash | 0x00120040 |
|
Default | 64 B |
| User boot area | 0xFF7F8000 | 
|
||
| Internal program flash | 0xFFF00000/0xFFF80000 |
|
Default | 512/1024 KB |
Debugger Authentication
If necessary, a debugger authentication via RX ID Code is performed as part of the connect sequence.
See article on Renesas RX cores for further information.
Debug Mode
When using FINE interface, a debug mode is enabled as part of the connect sequence and disabled on debug session close.
Enabling / disabling the debug mode requires writing to the flash.
See article on Renesas RX cores for further information.
Supported debug interfaces
The following debug interfaces are supported:
- JTAG
- FINE