Renesas RH850/U2C
The Renesas RH850/U2C (R7F702x) series of devices are Renesas (RH850)G4KH core based microcontrollers, for automotive applications.
Supported devices
Refer to the supported device list for a full list of all supported RH850/U2C family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG |  |
|
Flash banks
RH850/U2C2
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code Flash (User Area 0) | 0x0000_0000 | |
|
Default | 1 MB |
| Code Flash (User Area 1) | 0x0040_0000 | |
|
Default | 1 MB |
| Data Flash (Data Area 0) incl Extended Data Area (2KB @ 0xFF32_0000) | 0xFF20_0000 | |
|
Default | 130 KB |
| CSAf | 0xFF32_0800 | |
|
Default | 2 KB |
| CSAb | 0xFF32_1000 | |
|
Default | 2 KB |
| SSAf | 0xFF32_1800 | |
|
Default | 2 KB |
| SSAb | 0xFF32_2000 | |
|
Default | 2 KB |
| BPA0f | 0xFF32_2800 | |
|
Default | 2 KB |
| BPA0b | 0xFF32_3000 | |
|
Default | 2 KB |
RH850/U2C4
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code Flash (User Area 0) | 0x0000_0000 | |
|
Default | 2 MB |
| Code Flash (User Area 1) | 0x0040_0000 | |
|
Default | 2 MB |
| Data Flash (Data Area 0) incl Extended Data Area (2KB @ 0xFF32_0000) | 0xFF20_0000 | |
|
Default | 258 KB |
| CSAf | 0xFF32_0800 | |
|
Default | 2 KB |
| CSAb | 0xFF32_1000 | |
|
Default | 2 KB |
| SSAf | 0xFF32_1800 | |
|
Default | 2 KB |
| SSAb | 0xFF32_2000 | |
|
Default | 2 KB |
| BPA0f | 0xFF32_2800 | |
|
Default | 2 KB |
| BPA0b | 0xFF32_3000 | |
|
Default | 2 KB |
RH850/U2C8
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code Flash (User Area 0) | 0x0000_0000 | |
|
Default | 4 MB |
| Code Flash (User Area 1) | 0x0040_0000 | |
|
Default | 4 MB |
| Data Flash (Data Area 0) incl Extended Data Area (2KB @ 0xFF32_0000) | 0xFF20_0000 | |
|
Default | 258 KB |
| Data Flash (Data Area 1) | 0xFF24_0000 | |
|
Default | 128 KB |
| CSAf | 0xFF32_0800 | |
|
Default | 2 KB |
| CSAb | 0xFF32_1000 | |
|
Default | 2 KB |
| SSAf | 0xFF32_1800 | |
|
Default | 2 KB |
| SSAb | 0xFF32_2000 | |
|
Default | 2 KB |
| BPA0f | 0xFF32_2800 | |
|
Default | 2 KB |
| BPA0b | 0xFF32_3000 | |
|
Default | 2 KB |
Hardware Property Area
The Hardware Property Areas are implemented as normal flash banks and can be programmed like code flash or data flash.
However, there are a few things to be aware of:
- All Hardware Property Areas must be included in a single data file and programmed in a single programming procedure.
- When erasing front-side areas, the corresponding back-side areas are actually erased.
The internal sequence performed by the flashloader is as follows:
User programs front-side areas:
The back side of each included area is erased and programmed. Front side and back side are switched if the areas are valid.
User programs back-side areas:
The back side is erased and programmed normally.
Watchdog Handling
- The device has an Window Watchdog Timer (WDTB).
- The watchdog is fed during flash programming.
- Variable activation codes (VAC function) is not supported.
Security
IDCode authentication
In case debug authentication is required, the 32-byte IDCode needs to be set via the command SetCPUConnectIDCODE before connecting to the device:
J-Link>exec SetCPUConnectIDCODE FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF
If no IDCode is provided, the default IDCode (all 0xFF or 0x00) will be tried and used.
Limitations
- Challenge and Response authentication is not supported.
- Password Authentication for Data/Code flash is not supported.
Device Specific Handling
Reset
- The device uses normal RH850 core reset, no special handling necessary, like described here.
Attach
Attach is a debugging feature which exclusively applies to J-Link and J-Trace and does not apply to Flasher.
- Attach is not supported by default because the J-Link initializes certain RAM regions by default. RAM initialization can be disabled, see here
Multi-core support
Before proceeding with this article, please refer to the generic article regarding multi-core debugging here.
The RH850/U2C family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link support |
|---|---|
| PE0 |
|
| PE1 |
|
Below, the debug-related multi-core behavior of the J-Link is described for each core:
PE0 (Main core)
Init/Setup
- Initializes the ECC RAM
- Enables debugging
Reset
- Normal RH850 core reset is performed, no special handling necessary, like described here.
Attach
- Attach is not supported by default because the J-Link initializes certain RAM regions by default. RAM initialization can be disabled, see here
PE1 (Secondary core)
Init/Setup
- Initializes the ECC RAM
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
- Normal RH850 core reset is performed, no special handling necessary, like described here.
Attach
- Attach is not supported by default because the J-Link initializes certain RAM regions by default. RAM initialization can be disabled, see here