Renesas RA8E1

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The Renesas RA8E1 are Cortex-M85 based microcontrollers.

Flash Banks

Internal Flash

J-Link supports multiple loaders for the internal program flash bank. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.

Flash Bank Base address Size J-Link Support Loaders
Code flash option-setting memory (secure) 0x0300A100 384 B
  • Default
Code flash option-setting memory (non-secure) 0x1300A180 128 B
  • Default
  • OEM_PL1
  • RAMLess
Data flash option-setting memory 0x27030080 720 B
  • Default
Code flash (secure) 0x02000000 Up to 2048 KB
  • Default
  • DualBank
Code flash (non-secure) 0x12000000 Up to 2048 KB
  • Default
  • DualBank
  • OEM_PL1
  • RAMLess
Data flash (secure) 0x27000000 Up to 12 KB
  • Default
Data flash (non-secure) 0x37000000 Up to 12 KB
  • Default
  • OEM_PL1
  • RAMLess

Single Bank Mode

All loaders for the internal program flash bank, except the DualBank loader, require the device to be configured for single-bank (linear) mode via DUALSEL.BANKMD[2:0]. The configuration takes effect after a reset.

Dual Bank Mode

J-Link supports dual bank mode for the internal program flash bank. Notes on how to use the DualBank loader:

  • The device must be configured for dual-bank mode via DUALSEL.BANKMD[2:0]. The configuration takes effect after a reset.
  • The DualBank loader supports startup bank swapping.
  • The DualBank loader uses logical flash addresses for programming and erase operations. The hardware maps these addresses to the corresponding physical bank.
  • The user is responsible for ensuring that the desired physical bank is mapped to the expected logical address before programming.

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Flash programming in OSPI mode is supported for Infineon S28HL512T and S28HS512T only. Other flashes are handled in single/quad mode.

Bank name Base address Maximum size Supported pin configuration
External OSPI flash CS0 0x80000000 256 MB
  • Default
External OSPI flash CS1 0x90000000 256 MB
  • Default

For pin configurations, different from the ones mentioned above, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

Data flash specific handling

Data flash in erased state has undefined values, therefore when using J-Flash application, "Skip blank data" and "Perform blank check" options must be disabled in project settings.

Watchdog Handling

  • The device has two watchdogs: Watchdog Timer (WDT) and Independent Watchdog Timer (IWDT).
  • Both watchdogs are fed during flash programming.

Device Specific Handling

Connect

The connection sequence to RA8 devices is DLM-aware. The general DLM handling is described here and the family-specific handling is documented here.

Reset

  • The devices uses normal Cortex-M reset, no special handling necessary, like described here.
  • In case a normal Cortex-M reset fails, a pin reset + CPUWAIT bit is employed as fallback.

Device Initialization

Device initialization is implemented in the Device Provisioner utility: Renesas_RA8_Initialization.

Limitations

Using OEM_PL1 state with J-Flash

Since OEM_PL1 state requires the use of non-secure RAM (0x320D0000-0x320DFFFF), the user has to ensure that the J-Flash project is set up to use this RAM area instead of the secure RAM. By default J-Flash projects are created with secure RAM area (0x220D0000-0x220DFFFF) selected.

Evaluation Boards

Renesas FPB-RA8E1 evaluation board: http://wiki.segger.com/Renesas_FPB-RA8E1

Example Application

Renesas FPB-RA8E1 evaluation board: http://wiki.segger.com/Renesas_FPB-RA8E1#Example_Project

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