Renesas RA8

The RA8 series represents the highest-performance series within Renesas’ RA family, featuring advanced 32-bit MCUs based on the Arm Cortex-M85 core with clock speeds of up to 1 GHz. Selected RA8 devices also incorporate a dual-core architecture combining Cortex-M85 and Cortex-M33 cores.

This article provides information applicable across the entire RA8 product series. Information which is more specific to the respective MCU groups (e.g. RA8M2, RA8D2, RA8P1, ...) is provided in group specific articles. A list of all Renesas devices supported by SEGGER can be found here For further information regarding the RA8 series, please refer to the website and documentation by Renesas.

Connecting to Dual-Core RA8x2 Targets

In dual-core RA8x2 devices, the primary CPU can be swapped. By default, CPU0 (Cortex-M85) is configured as the primary core and is started first after reset. In this default configuration, connection and debugging proceed as described for standard RA8 devices.

The primary CPU can be permanently switched to CPU1 (Cortex-M33) while the device is in boot mode using the serial programming interface (e.g., via Renesas Flash Programmer and the Parameter Setting Command). Once this change is made, CPU1 becomes the primary CPU at boot.

After switching the primary CPU, the user must update the "Device Configuration Information Register for Debug" register in the option-setting memory located at address 0x02C9F04C. This register needs to be updated at bit position 0 to reflect the new primary CPU. The bit at position 0 indicates which CPU is considered primary and J-Link queries this bit to steer debug behavior appropriately:

• 0 = CPU1 (Cortex-M33)
• 1 = CPU0 (Cortex-M85, default)

A mismatch between the configured bit and the actual primary CPU can result in failed or unstable debug connections.

The configuration bit can be updated using Renesas Flash Programmer, J-Flash or equivalent tools. For example, using the Renesas Flash Programmer CLI:

rfp-cli -d RA -if swd -tool jlink -writebit 0x02c9f04c 0 0  // Configures CPU1 (Cortex-M33) as primary
rfp-cli -d RA -if swd -tool jlink -writebit 0x02c9f04c 0 1  // Configures CPU0 (Cortex-M85) as primary
rfp-cli -d RA -if swd -tool jlink -read-view 0x02c9f04c 4   // Confirm that bit at position 0 was configured as intended

Unlike the one-time switch of the primary CPU via boot firmware, this configuration bit can be modified as needed. After ensuring the bit correctly reflects the active primary CPU, the debug connection can be established as usual or as described in RA8 group specific articles.

Please note: Official documentation from Renesas is not expected until Q3/2026.