Renesas RA2T1
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The Renesas RA2T1 are energy-efficient microprocessors based on the Cortex-M23 core, well suited for cost-sensitive and low-power applications.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Program flash | 0x0000_0000 | 64 KB | 
|
| Option-setting memory | 0x0101_0010 | 36 B |
|
| Data flash | 0x4010_0000 | 2 KB |
|
Watchdog Handling
- The device has two watchdogs WDT and IWDT.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
Security
- The device have a debug locking feature based on the 128 bit IDCODE, programmed into option-setting memory.
- During connection, the user will be asked to specify the IDCODE code to unlock debuging access if it was previously programmed.
Flash write protection
- The device implemets a program flash write protection feature based on the access window. A pair of addresses can be programmed into option-setting memory to determine a memory range, in which programming/erasing operations are permited.
- To disable flash protection using JLink commander:
exec EnableEraseAllFlashBanks erase 0x01010010 0x01010034
- To disable flash protection using JFlash application:
1) Select "Opt flash" bank only. 2) Click Target -> Manual Programming -> Erase Sectors
- If FSPR bit of AWS register is set to 0, program flash write protection is enabled permanently.