Renesas RA2L2
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The Renesas RA2L2 are energy-efficient microprocessors based on the Cortex-M23 core, well suited for cost-sensitive and low-power applications.
Flash Banks
Internal Flash
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code Flash | 0x00000000 |  |
|
Default | Up to 128 KB |
| Opt Flash | 0x01010010 | |
|
Default | 36 B |
| Data Flash | 0x40100000 | |
|
Default | 4 KB |
Watchdog Handling
- The device has two watchdogs WDT and IWDT.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
Security
- The device has a debug locking feature based on the 128 bit IDCODE, programmed into option-setting memory.
- During connection, the user will be asked to specify the IDCODE code to unlock debugging access if it was previously programmed.
- Use the following IDCODE to send the ALeRASE command, which triggers erasure of the user flash (code and data) area and the configuration area: FFFFFFFFFFFFFFFFFF45534152654C41
- Important: Make sure the byte order of the ALeRASE command is correct, as above shown above. A common mistake is using the wrong byte order, which will cause the command to fail.
Flash write protection
- The device implements a program flash write protection feature based on the access window. A pair of addresses can be programmed into option-setting memory to determine a memory range, in which programming/erasing operations are permitted.
- To disable flash protection using JLink commander:
exec EnableEraseAllFlashBanks erase 0x01010010 0x01010034
- To disable flash protection using JFlash application:
1) Select "Opt flash" bank only. 2) Click Target -> Manual Programming -> Erase Sectors
- If FSPR bit of AWS register is set to 0, program flash write protection is enabled permanently.