RA6M4
The Renesas RA6M4 series are microcontrollers based on the ARM Cortex-M33 core.
Supported devices
Refer to the supported device list for a full list of all supported RA6M4 family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| SWD |  |
|
| JTAG | |
|
Flash Banks
Internal Flash
J-Link supports multiple loaders for the internal program flash bank. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Internal option-setting memory | 0x0100A100 | |
|
Default | 512 bytes |
| Internal program flash | 0x00000000 | |
|
Default | Up to 1MB |
| RAMLess | Up to 1MB | ||||
| DualBank | Up to 1MB | ||||
| Internal data flash | 0x08000000 | |
|
Default | 8 KB |
Single Bank Mode
All loaders for the internal program flash bank, except the DualBank loader, require the device to be configured for single-bank (linear) mode via DUALSEL.BANKMD[2:0]. The configuration takes effect after a reset.
Dual Bank Mode
J-Link supports dual bank mode for the internal program flash bank. Notes on how to use the DualBank loader:
- The device must be configured for dual-bank mode via DUALSEL.BANKMD[2:0]. The configuration takes effect after a reset.
- The DualBank loader supports startup bank swapping.
- The DualBank loader uses logical flash addresses for programming and erase operations. The hardware maps these addresses to the corresponding physical bank.
- The user is responsible for ensuring that the desired physical bank is mapped to the expected logical address before programming.
External QSPI flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for this device. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| External QSPI flash | 0x60000000 | |
|
CLK@P305_nCS@P306_D0@P307_D1@P308_D2@P309_D3@P310 | 64 MB |
| CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505 | 64 MB | ||||
| CLK@P214_nCS@P207_D0@P211_D1@P210_D2@P209_D3@P208 | 64 MB | ||||
| CLK@P100_nCS@P112_D0@P102_D1@P101_D2@P104_D3@P103 | 64 MB | ||||
For pin configurations, different from the ones mentioned above, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
Device Initialization
Device initialization is implemented in the Device Provisioner utility: Renesas_RA6_Initialization.
Minimum requirements
The Renesas RA6M4 series devices requires special handling for the TrustZone partition registers of the MCU. This requires certain HW support which is not provided by older J-Link models. The following table lists the minimum J-Link HW version needed to support this MCU.
- J-Link-OB-S124
- J-Link BASE V10
- J-Link PLUS V10
- J-Link ULTRA+ V4
- J-Link PRO V4
- J-Link WiFi V1
- J-Trace PRO V2 Cortex-M
- J-Trace PRO V2 Cortex
Later versions (e.g. V10 is listed and current HW is V11) will also work.
Note: Models which are not listed here do not support this MCU.
Tracing on RA6M4 series
Tracing on Renesas R7FA6M4
Minimum requirements
In order to use trace on the Renesas R7FA6M4 MCU devices, the following minimum requirements have to be met:
- J-Link software version V7.92h or later
- Ozone V3.30b or later (if streaming trace and / or the sample project from below shall be used)
- SEGGER Embedded Studio V7.30
- J-Trace PRO for Cortex-M HW version V2.0 or later for streaming trace
- J-Link Plus V10 or later for TMC/ETB trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Streaming trace
The project has been tested with the minimum requirements mentioned above and a Renesas EK-RA6M4.
Example project: Renesas_R7FA6M4_TracePins.zip
Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Trace buffer (TMC/ETB)
Example Project: Renesas_R7FA6M4_TraceBuffer.zip
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
