NXP i.MX RT700
The NXP i.MXRT700 are multi-core MCUs consisting of two Cortex-M33 and one RISC-V cores.
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
For a complete list of supported flash devices, please refer to the Supported SPI Flashes page on our website.
| Bank | Base address | Maximum size |
|---|---|---|
| XSPI1 | 0x08000000 | 128 MB |
| XSPI1 (secure) | 0x18000000 | 128 MB |
| XSPI0 | 0x28000000 | 128 MB |
| XSPI0 (secure) | 0x38000000 | 128 MB |
Watchdog Handling
- The watchdogs WWDT0 and WWDT1 are fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MXRT700 family comes with multiple cores, of which the following are supported:
| Core | J-Link Support |
|---|---|
| Cortex-M33 (CPU0) | 
|
| Cortex-M33 (CPU1) |
|
| RISC-V (EZH-V) |
|
Device Specific Handling
Connect
Debug access is enabled through debug mailbox.
Reset
The device uses custom reset to ensure that the boot ROM is executed. Afterwards debug access is reenabled.
Evaluation Boards
Example Application
Tracing
This section will provide an overview of the available trace types on this device.
On-chip trace
This device supports so-called on-chip tracing via trace buffer.
For this device this feature works out-of-the-box. Simply select trace buffer as the trace source in your IDE or debug software and you should see trace data recordings when running and halting your application.
Off-chip trace
This device supports so-called off-chip tracing via TPIU.
Off-chip tracing on this device does not work out-of-the-box and requires additional init steps which are explained here.