NXP i.MX 94
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The NXP iMX 94 are applications processors integrating up to 4 Arm Cortex-A55 cores, 2 ARM Cortex-M7, 2 ARM Cortex-M33, Neutron Neural Processing Unit and Edgelock secure enclave security.
Flash Banks
Cortex-A55
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| QSPI Flash [1] | 0x28000000 |  |
|
Default | 128 MB |
- ↑ QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Limitations
- In order to use QSPI flashloader, device must be booted using the following boot image:File:NXP iMX94 boot.bin
It should be written to one of the boot media, e.g. SD card:
dd if=NXP_iMX94_boot.bin of=/dev/sdc bs=1024 seek=32; sync
QSPI flash
The QSPI flashloader uses the following pin configuration:
| Alternate function | Port / Pin |
|---|---|
| CLK | XSPI1_CLK |
| nCS | XSPI1_SS0B |
| IO0 | XSPI1_DATA0 |
| IO1 | XSPI1_DATA1 |
| IO2 | XSPI1_DATA2 |
| IO3 | XSPI1_DATA3 |
ECC RAM
- ECC TCM and ECC Cache features of Cortex-M33 are enabled during connecting to the target device.
Configurable TCM size
- User application should ensure configured TCM size before using it.
Multi-Core Support
- Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The iMX 94 family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link Support |
|---|---|
| 4x Cortex A-55 |
|
| 2x Cortex M-33 |
|
| 2x Cortex M-7 |
|
| 1x Neutron NPU | 
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A55
Init/Setup
- Cortex-A55 cores must be enabled by the bootloader before it can be used for debugging.
Reset
- Core reset is not performed.
Attach
- Attach to a running target is supported only assuming it is already configured by bootloader/OS kernel.
Cortex-M7
Init/Setup
- Cortex-M7 clock must be enabled by the bootloader/OS kernel before it can be used for debugging.
Reset
- Core reset is not performed.
Attach
- Attach is supported.
Cortex-M33
Init/Setup
- The target device must contain a valid boot-image that performs initial configuration and enables debug access.
Reset
- Core reset is not performed.
Attach
- Attach is supported.
Device Specific Handling
Limitations
- Some U-Boot/Linux images can reconfigure SWD/JTAG pins restricting access to the debug components. Please refer to the corresponding silicon/board vendor in order to get information about SWD/JTAG configuration.
- The Cortex-A55 Application domain is held in reset until the EdgeLock Enclave (ELE) successfully authenticates an AHAB boot container. Therefore, a valid boot image must be programmed into one of the supported boot media (e.g. SD card),
or downloaded via the Serial Download Protocol (SDP), before the Cortex-A55 cores can be released from reset.