NXP S32K5xx
The NXP S32K5 are multicore microcontrollers.
Supported devices
Refer to the supported device list for a full list of all supported S32K5 family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| SWD |  |
|
| JTAG | |
|
Flash Banks
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| MRAM | 0x08000000 | |
|
Default | 32 MB |
| XSPI [1] | 0x81000000 |  |
|
- | - |
- ↑ QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Watchdog Handling
- The device has a watchdog LPE_SWT.
- The watchdog can be configured in normal or window mode.
- If it is configured in normal mode, the watchdog is fed during flash programming.
- If it is configured in window mode, the watchdog is fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The S32K5 family comes with a variety of multi-core options.
| Core | J-Link Support |
|---|---|
| Cortex-M4 |
|
| Cortex-M7_0 |
|
| Cortex-M7_1 |
|
| Cortex-M7_2 |
|
| Cortex-M7_3 |
|
| Cortex-R52_0 |
|
| Cortex-R52_1 |
|
Below, the debug-related multi-core behavior of the J-Link is described for each core:
Main core (Cortex-M4)
Init/Setup
- Enables debugging
Reset
- Device-specific reset is performed using the Peripheral Reset LP Core register
Secondary cores (Cortex-M7)
Init/Setup
- Enables debugging
- Initializes HyperRAM during InitTarget() phase.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
Secondary cores (Cortex-R52)
Init/Setup
- Enables debugging
Reset
- No reset is performed.
- A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.
Evaluation boards
Example application
Tracing on NXP S32K566
This section describes how to get started with trace on the NXP S32K566 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracingMinimum requirements
In order to use trace on the NXP S32K566 MCU devices, the following minimum requirements have to be met:
- J-Link software version V9.40 or later
- Ozone V3.40h or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO version V3.0 or later for streaming (off-chip) trace
- J-Link Plus V12 or later for buffer (on-chip) trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.24. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Cortex-M4
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_M4_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-M7_0
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_M7_0_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-M7_1
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_M7_1_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-M7_2
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_M7_2_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-M7_3
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_M7_3_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-R52_0
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_R52_0_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.
Cortex-R52_1
The project below has been tested with the minimum requirements mentioned above and a .
- Example project: NXP_S32K566_R52_1_TraceExample.zip
Streaming trace
Open the *_TracePins.jdebug project contained in the example project in Ozone.
Trace buffer
Open the *_TraceBuffer.jdebug project contained in the example project in Ozone.