NXP MCX L
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The NXP MCX L are dual core ARM Cortex-M33/Cortex-M0+ microprocessors.
Supported devices
Refer to the supported device list for a full list of all supported MCX L family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| JTAG |  |
|
| SWD | |
|
Flash banks
MCX L142
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Program Flash(NS) | 0x00000000 | |
|
Default | 64 KB |
| CMPA(NS)[1] | 0x003E0000 | |
|
Default | 8 KB |
| Program Flash(S) | 0x10000000 | |
|
Default | 64 KB |
| CMPA(S)[1] | 0x103E0000 | |
|
Default | 8 KB |
MCX L143/L253
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Program Flash(NS) | 0x00000000 | |
|
Default | 128 KB |
| CMPA(NS)[1] | 0x003E0000 | |
|
Default | 8 KB |
| Program Flash(S) | 0x10000000 | |
|
Default | 128 KB |
| CMPA(S)[1] | 0x103E0000 | |
|
Default | 8 KB |
MCX L144/L254
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Program Flash(NS) | 0x00000000 | |
|
Default | 256 KB |
| CMPA(NS)[1] | 0x005E0000 | |
|
Default | 8 KB |
| Program Flash(S) | 0x10000000 | |
|
Default | 256 KB |
| CMPA(S)[1] | 0x105E0000 | |
|
Default | 8 KB |
MCX L255
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Program Flash(NS) | 0x00000000 | |
|
Default | 408 KB |
| Secure Installer(NS) | 0x00066000 | |
|
Default | 96 KB |
| CMPA(NS)[1] | 0x007E0000 | |
|
Default | 8 KB |
| Program Flash(S) | 0x10000000 | |
|
Default | 408 KB |
| Secure Installer(S) | 0x10066000 | |
|
Default | 96 KB |
| CMPA(S)[1] | 0x107E0000 | |
|
Default | 8 KB |
Flash programming is only available for Main Core.
ECC Flash
- Device has ECC Flash, but no special handling required.
Secure Installer
- Some derivatives come with a secure installer(SI).
- The secure installer can be deleted by the Device Provisioner: MCX A SiErase .
- When this secure installer is removed, a device unique token is present in the CMPA area.
Warning:
This device unique token has to be has to be resident forever in the CMPA area, otherwise the device will be bricked.
This device unique token has to be has to be resident forever in the CMPA area, otherwise the device will be bricked.
CMPA
- CMPA area contains device configuration data.
- Not correct programmed data may brick the device.
Watchdog Handling
- The device has two watchdogs: WWDT and CDOG.
- The watchdog WWDT is fed during flash programming.
- No handling for CDOG implemented.
Multi-core support
Before proceeding with this article, please check out the generic article regarding multi-core debugging here.
| Core | J-Link support |
|---|---|
| Cortex-M33 |
|
| Cortex-M0+ |
|
Below the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M33 (Main core)
Init/Setup
- If debugging is not enabled yet, the enable debug sequence is executed.
Reset
- Device specific reset is performed, according to Halting execution immediately following ROM execution from reference manual.
- SRAM A2 is set to RWX.
Flash programming
- Programming of all flash banks is supported.
Attach
- Attach is supported
Cortex-M0+ (Secondary core)
Init/Setup
- If debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled and a dummy application is load to RAM.
Reset
- A device specific reset is executed and the core is halted at application entry.
Flash programming
- Not supported.
Attach
- Attach is supported.