NXP MCX L

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The NXP MCX L are dual core ARM Cortex-M33/Cortex-M0+ microprocessors.

Flash Banks

Internal Flash

Flash Bank Base address Size J-Link Support
Program Flash(NS)[1] 0x00000000 up to 512 KB YES.png
Program Flash(S)[1] 0x10000000 up to 512 KB YES.png
  1. ↑ 1.0 1.1 Careful: The last sector contains CMPA/option byte region. Programming incorrect data may brick the device.

ECC Flash

  • Device has ECC Flash, but no special handling required.

Watchdog Handling

  • The device has two watchdogs: WWDT and CDOG.
  • The watchdog WWDT is fed during flash programming.
  • No handling for CDOG implemented.

Reset

  • The J-Link performs a device specific reset sequence. SRAM A2 is set to RWX.

Attach

Attach is supported.

Evaluation Boards

Example Application

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