NXP MCX E3
The NXP MCX E3 are Cortex-M7 based MCUs in single or dual core configurations.
Supported devices
Refer to the supported device list for a full list of all supported MCX E3 family devices, their corresponding names and connection diagrams.
Target interfaces
| Interface | J-Link support | Flasher support |
|---|---|---|
| SWD |  |
|
| JTAG |  |
|
Flash banks
MCXE315
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code flash 0 | 0x00400000 | |
|
Default | 464 KB |
| Data flash | 0x10000000 | |
|
Default | 64 KB |
| UTEST (OTP) | 0x1B000000 | |
|
Default | 8 KB |
MCXE316
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code flash 0 | 0x00400000 | |
|
Default | 512 KB |
| Code flash 1 | 0x00500000 | |
|
Default | 464 KB |
| Data flash | 0x10000000 | |
|
Default | 64 KB |
| UTEST (OTP) | 0x1B000000 | |
|
Default | 8 KB |
MCXE317, MCXE327
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code flash 0 | 0x00400000 | |
|
Default | 1 MB |
| Code flash 1 | 0x00500000 | |
|
Default | 976 KB |
| Data flash | 0x10000000 | |
|
Default | 128 KB |
| UTEST (OTP) | 0x1B000000 | |
|
Default | 8 KB |
MCXE31B, MCXE32B
| Flash bank | Base address | J-Link support | Flasher support | Loader | |
|---|---|---|---|---|---|
| Name | Bank size | ||||
| Code flash 0 | 0x00400000 | |
|
Default | 1 MB |
| Code flash 1 | 0x00500000 | |
|
Default | 1 MB |
| Code flash 2 | 0x00600000 | |
|
Default | 1 MB |
| Code flash 3 | 0x00700000 | |
|
Default | 976 KB |
| Data flash | 0x10000000 | |
|
Default | 128 KB |
| UTEST (OTP) | 0x1B000000 | |
|
Default | 8 KB |
RAM
The ITCM, DTCM and SRAM must be properly initialized with correct ECC before any read operation to avoid any code runaway or software malfunction or core lockup. ITCM must be initialized with 64-bit writes whereas DTCM can be initialized with 32-bit or 64-bit writes. The following memory ranges are initialized by the J-Link on connect by default. Other ranges needs to be initialized by the application / boot ROM.
| Memory | Address | Size |
|---|---|---|
| ITCM0 | 0x00000000 | 32 KB |
| DTCM0 | 0x20000000 | 32 KB |
| SRAM0 | 0x20400000 | 16 KB |
Initialization of the work RAM is skipped in case the attach feature of J-Link is used (exec ForceAttachTarget=1)
Watchdog handling
- The device has up to 2 watchdogs (SWT0, SWT1) depending on the specific MCU and number of Cortex-M7 cores.
- If the watchdog of the core connected to is enabled, it is turned off during flash programming and turned back on afterwards.
Device specific handling
Connect
- If debugging is not enabled yet, the enable debug sequence is executed.
- If a connection is not otherwise possible, a connect under reset is performed. See Reset
Reset
- The J-Link performs a device specific reset sequence. The reset is executed for the main core, only. Reset of the main core, resets / disables the secondary core if used in parallel.
Attach
Attach is a debugging feature which exclusively applies to J-Link and J-Trace and does not apply to Flasher.
- Attach is supported if RAM initialization is skipped.
Security
HSE firmware is present and located at the end of the last code flash memory. Access to this region is prohibited.
Multi-core support
Before proceeding with this article, please refer to the generic article regarding multi-core debugging here.
The MCX E3 family comes with a variety of multi-core options.
Some of the are available with enabled lockstep mode, only.
| Core | J-Link support |
|---|---|
| M7_0 |
|
| M7_1 |
|
Below, the debug-related multi-core behavior of the J-Link is described for each core:
M7_0 (Main core)
Init/Setup
Reset
- Device specific reset is performed, see Reset
Attach
- Attach is supported, see Attach
M7_1 (Secondary core)
Init/Setup
- Initializes the ECC RAM, see RAM
- Enables debugging, see Connect
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
- A generic reset of this core is currently not supported by J-Link. This means that a core reset is not performed when issued by a debugger (e.g. SEGGER Ozone).
If a reset of this core is required, this needs to be implemented via a customized ResetTarget() J-Link script file function.
If you are interested in a customized ResetTarget() implemented by SEGGER, please get in touch with us directly: https://www.segger.com/support/technical-support/.
Attach
- Attach is supported, see Attach
Debug Authentication
If the HSE is setup for password authentication, you can provide it in 2 ways:
Specifying the authentication code using J-Link Command String
This is the recommended method as the specified authentication key will be used for the whole session. This way, the key must not specified multiple times (e.g. if a reset is performed). The J-Link Command String needs to be passed to the J-Link DLL before establishing the target connection. The J-Link Command String SetCPUConnectIDCode <AuthKey> has to be used (see example below).
Example authentication key:
- AuthenticationKey0: 0x01234567
- AuthenticationKey1: 0x89ABCDEF
- AuthenticationKey2: 0x00224466
- AuthenticationKey3: 0x88AABBCC
exec SetCPUConnectIDCODE 67452301EFCDAB8966442200CCBBAA88
Specifying the authentication code using the ID Code dialog
If the authentication key has not been specified using the Command String although it is required to enable debug access, the following message box will pop up which allows specifying the authentication key.
