NXP KW47
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The NXP KW47 are single/dual core ARM Cortex-M33 microprocessors for wireless applications.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal Flash(NS) | 0x00000000 | up to 2 MB | 
|
| Internal Flash(S) | 0x10000000 | up to 2 MB |
|
| NBU Flash (via Core 0) | 0x48800000 | 512 KB | [1]
|
| NBU Flash (via Core 1) | 0x00000000 | 512 KB | [1]
|
Flash programming is only supported on M33 core 0.
Watchdog Handling
- The device has 1 watchdog.
- The watchdog is fed during flash programming on Core 0.
ECC RAM
- J-Link initializes on connect to M33 Core 0 32KB RAM at address 0x30004000.
- No init is done on connect to M33 Core 1.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The KW47 family comes with a second NBU radio core(Core 1)on some derivates.
This is disabled after reset / by default.
| Core | J-Link Support |
|---|---|
| M33 Core 0 |
|
| M33 Core 1 (NBU / Radio) |
|
In below, the debug related multi-core behavior of the J-Link is described for each core:
M33 Main core 0
Init/Setup
- Initializes the ECC RAM
- Enables debugging
Reset
- Device specific reset is performed.
Attach
- Attach is supported if attach mode is forced, details can be found here.
M33 secondary core 1 (NBU / Radio)
Init/Setup
- If debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / released from reset-
Reset
- The core is reset via core 0 peripheral RF2P4GHZ_CTRL.
Attach
- Attach is supported.
Evaluation Boards
KW-MCXW-EVK-MB X-KW47-001-M10 evaluation boards