Infineon S6J3360 S6J3370
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The Infineon T1G S6J3360/S6J3370 are 32-bit RISC microcontrollers with an Arm Cortex-R5 core.
Flash Banks
| Flash Bank | Base address | J-Link Support | Loader | |
|---|---|---|---|---|
| Name | Size | |||
| Program Flash | 0x019F0000 | 
|
Default | Up to 2112 KB |
| Work Flash | 0x0E000000 |
|
Default | 112 KB |
ECC RAM
- TCRAM is initialized with 0s upon connect in order to generate correct ECC values.
Watchdog Handling
- The device has a watchdog HWDG.
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
Reset
- The device uses software trigger hard reset signal SWHRST to reset the CPU.
Limitations
Attach
- Attach is not supported by default because the J-Link initializes certain RAM regions by default.
Security
- The device have security options called "Markers" that are located in the program flash range 0x019F0000 - 0x019F0150. Writing wrong values to the security markers can permanently lock the device.