Geehy G32R501xx

The Geehy G32R501 series devices are energy-efficient microprocessors based on the Cortex-M52 core, well suited for cost-sensitive and low-power applications.

Flash Banks

G32R501xxC

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Dual Bank	256 KB
			Single Bank	256 KB

G32R501xxY

Flash Bank	Base address	J-Link Support	Loader
			Name	Size
Internal Flash	0x08000000		Dual Bank	640 KB
			Single Bank	640 KB

Watchdog Handling

• The device has a watchdog WDT.
• The watchdog is fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The G32R501 family comes with single core and dual core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
In below, the debug related multi-core behavior of the J-Link is described for each core:

M52_0

Init/Setup

If the M52 is held in reset, J-Link releases the core from reset.

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

Attach

• Attach is possible in case of the M52 core is clocked and released from reset.

M52_1

Init/Setup

If the M52 is held in reset, J-Link releases the core from reset.

Reset

• Reset of core 1 is not supported.

Attach

• Attach is possible in case of the M52 core is clocked and released from reset.

Evaluation Boards

• Geehy G32R501 EVAL

Example Application

• Geehy G32R501 EVAL