Flasher - Glossary

This chapter describes important terms used throughout this manual.

Big-endian
Memory organization where the least significant byte of a word is at a higher address than the most significant byte. See Little-endian.

Cache cleaning
The process of writing dirty data in a cache to main memory.

Coprocessor
An additional processor that is used for certain operations, for example, for floating-point math calculations, signal processing, or memory management.

Dirty data
When referring to a processor data cache, data that has been written to the cache but has not been written to main memory is referred to as dirty data. Only write-back caches can have dirty data because a write-through cache writes data to the cache and to main memory simultaneously. See also cache cleaning.

Halfword
A 16-bit unit of information.

Host
A computer which provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.

ICache
Instruction cache.

ID
Identifier.

IEEE 1149.1
The IEEE Standard which defines TAP. Commonly (but incorrectly) referred to as JTAG.

Image
An executable file that has been loaded onto a processor for execution.

Instruction Register
When referring to a TAP controller, a register that controls the operation of the TAP.

IR
See Instruction Register.

Joint Test Action Group (JTAG)
The name of the standards group which created the IEEE 1149.1 specification.

Little-endian
Memory organization where the least significant byte of a word is at a lower address than the most significant byte. See also Big-endian.

Memory coherency
A memory is coherent if the value read by a data read or instruction fetch is the value that was most recently written to that location. Obtaining memory coherency is difficult when there are multiple possible physical locations that are involved, such as a system that has main memory, a write buffer, and a cache.

Memory management unit (MMU)
Hardware that controls caches and access permissions to blocks of memory, and translates virtual to physical addresses.

Memory Protection Unit (MPU)
Hardware that controls access permissions to blocks of memory. Unlike an MMU, a MPU does not translate virtual addresses to physical addresses.

RESET
Abbreviation of System Reset. The electronic signal which causes the target system other than the TAP controller to be reset. This signal is also known as "nSRST" "nSYSRST", "nRST", or "nRESET" in some other manuals. See also nTRST.

nTRST
Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some other manuals. See also nSRST.

Open collector
A signal that may be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a "wired AND" signal.

Processor Core
The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit, and the register bank. It excludes optional coprocessors, caches, and the memory management unit.

Remapping
Changing the address of physical memory or devices after the application has started executing. This is typically done to make RAM replace ROM once the initialization has been done.

RTOS
Real Time Operating System.

TAP Controller
Logic on a device which allows access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1.

Target
The actual processor (real silicon or simulated) on which the application program is running.

TCK
The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO.

TDI
The electronic signal input to a TAP controller from the data source (upstream). Usually, this is seen connecting the J-Link Interface Unit to the first TAP controller.

TDO
The electronic signal output from a TAP controller to the data sink (downstream). Usually, this is seen connecting the last TAP controller to the J-Link Interface Unit.

Test Access Port (TAP)
The port used to access a device's TAP Controller. Comprises TCK, TMS, TDI, TDO, and nTRST (optional).

Transistor-transistor logic (TTL)
A type of logic design in which two bipolar transistors drive the logic output to one or zero. LSI and VLSI logic often used TTL with HIGH logic level approaching +5V and LOW approaching 0V.

Word
A 32-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.