Flasher - Glossary

Welcome to the glossary section, where key terms related to SEGGER's J-Link, J-Trace and Flasher portfolio are defined for easy reference.

This glossary is a living article and will be updated regularly with additional terms and definitions.

A

Access Protocol

The interface and communication protocol used by the Flasher to communicate with the target and perform the flash algorithm.

ASCII Command Interface

See #Command Line Interface (CLI)

B

Big-endian

Memory organization where the least significant byte of a word is at a higher address than the most significant byte. See Little-endian.

C

Cache cleaning

The process of writing dirty data in a cache to main memory.

Command Instance

See #Command Program.

Command Line Interface (CLI)

A text-based interface to interact with the Flasher remotely. Beside commands to carry out common operations like programming the connected target, further commands, like selecting one of the #Flasher Project's stored on the Flasher, are available.

Command Program

A tool that can be used for the standalone mode to trigger operations on the Flasher. This can be, for instance, a tool that generates a positive pulse (5V–30V) on pin 1 of the SUBD9 male connector that starts the #AUTO command for the currently selected #Flasher Project or a tool sending commands via the #Command Line Interface (CLI).

Configuration Program

The program (U-Flash or J-Flash) used to generate the #Project Configuration.

Control Instance

See #Control Program.

Control Program

An application used to provides information like the data from the target image and the steps to execute the flash algorithm to a programmer. This is comparable to J-Flash if it is being used in host-based aka. PC-controlled mode. When the Flasher is used in standalone mode, a control program is not required.

Coprocessor

An additional processor that is used for certain operations, for example, for floating-point math calculations, signal processing, or memory management.

D

Device Definition File (DDF)

Device definition files are XML files used with U-Flash to define support, device properties, and configuration including dialog elements for devices.

Dirty data

When referring to a processor data cache, data that has been written to the cache but has not been written to main memory is referred to as dirty data. Only write-back caches can have dirty data because a write-through cache writes data to the cache and to main memory simultaneously. See also cache cleaning.

F

File Access Mode

The mode in which the Flasher acts as a mass storage USB device. This mode is entered by connecting the Flasher while the PROG button is pressed. For more information, please refer to UM08022 Flasher#File access mode.

Functional Circuit Test (FCT)

The last test for fully assembled PCBs, assessing overall functionality by subjecting the device to input signals and evaluating corresponding output responses.

Flasher Configuration

The Flasher Configuration consists of all #Flasher Project's and the #Flasher Settings located on the Flasher.

Flasher Project

A project located on the Flasher consisting of the #Project Configuration and the #Project Operation Data. This project is able to carry out operations like programming the connected target. Please note that changes made to the Flasher Project located on the Flasher will be overwritten if the master #Flasher Configuration is sent to the Flasher again.

Flasher Settings

Files that belong to the Flasher Settings are the Flasher.ini, which specifies the currently active #Flasher Project, the Secure.ini, the Flasher.log and the Firmware.bin used to update the Flasher firmware.

H

Halfword

A 16-bit unit of information.

Handshake Control

A remote control interface to trigger the #AUTO Flasher operation and to get OK and BUSY status using 3 lines of the serial interface (SUBD9 male connector).

Host

A computer which provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.

Host-based Mode

The counterpart of the #Standalone Mode which requires a #Control Program to carry out an operation like programming the connected target.

I

ICache

Instruction cache.

ID

Identifier.

IEEE 1149.1

The IEEE Standard which defines TAP. Commonly (but incorrectly) referred to as JTAG.

Image

An executable file that has been loaded onto a processor for execution.

In-Circuit Test (ICT)

An electronic testing method that verifies individual components and connections on a printed circuit board during manufacturing, detecting defects like short circuits and incorrect values.

Instruction Register

When referring to a TAP controller, a register that controls the operation of the TAP.

IR

See Instruction Register.

J

Joint Test Action Group (JTAG)

The name of the standards group which created the IEEE 1149.1 specification.

L

Little-endian

Memory organization where the least significant byte of a word is at a lower address than the most significant byte. See also Big-endian.

M

Mass Storage Device (MSD)

A device that can be used as a storage medium. The Flasher supports a mode in which it acts as a USB MSD (see #File Access Mode) to manage the standalone #Flasher Projects stored in its internal file system.

Memory coherency

A memory is coherent if the value read by a data read or instruction fetch is the value that was most recently written to that location. Obtaining memory coherency is difficult when there are multiple possible physical locations that are involved, such as a system that has main memory, a write buffer, and a cache.

Memory management unit (MMU)

Hardware that controls caches and access permissions to blocks of memory, and translates virtual to physical addresses.

Memory Protection Unit (MPU)

Hardware that controls access permissions to blocks of memory. Unlike an MMU, a MPU does not translate virtual addresses to physical addresses.

N

nTRST

Abbreviation of TAP Reset. The electronic signal that causes the target system TAP controller to be reset. This signal is known as nICERST in some other manuals. See also nSRST.

O

Open collector

A signal that may be actively driven LOW by one or more drivers, and is otherwise passively pulled HIGH. Also known as a "wired AND" signal.

P

PC-controlled Mode

See #Host-based Mode.

Processor Core

The part of a microprocessor that reads instructions from memory and executes them, including the instruction fetch unit, arithmetic and logic unit, and the register bank. It excludes optional coprocessors, caches, and the memory management unit.

Project Configuration

The files generated by the #Configuration Program that are sent to the Flasher plus the SNList.txt. Once the Project Configuration is on the Flasher, it is part of the #Flasher Project and can't be used to restore the Project Configuration, because the Project Configuration in the #Flasher Project might have been modified by the user.

Project Operation Data

The Serial.txt, Patches.txt and Cntdown.txt located in a #Flasher Project.

Public Area

A volume in the Flasher's file system where a #Flasher Configuration can be stored and accessed by everyone. See also #Secure Area.

R

Remapping

Changing the address of physical memory or devices after the application has started executing. This is typically done to make RAM replace ROM once the initialization has been done.

RESET

Abbreviation of System Reset. The electronic signal which causes the target system other than the TAP controller to be reset. This signal is also known as "nSRST" "nSYSRST", "nRST", or "nRESET" in some other manuals. See also nTRST.

RTOS

Real Time Operating System.

S

Secure Area

A volume in the Flasher's file system where a Flasher configuration can be stored that can't be read out anymore. For more information, please refer to UM08022_Flasher#Authorized flashing.

Standalone Mode

A mode in which all required files are located on the Flasher and no additional #Control Program is required to carry out an operation like programming the connected target. How to command the Flasher in Standalone Mode https//wiki.segger.com/UM08022_Flasher#Remote_control

T

TAP Controller

Logic on a device which allows access to some or all of that device for test purposes. The circuit functionality is defined in IEEE1149.1.

Target

The actual processor (real silicon or simulated) on which the application program is running.

Target Encrypted Link Package (TELP)

A package, used with the Flasher Secure and Flasher Secure Server, providing an encrypted transfer of the firmware from the Flasher Secure to the target.

Target Image

The file containing the firmware to be programmed into the target. A target image can be stored using a variety of different file types. The Flasher uses a special file type for the target image with .DAT extension, which is generated by the #Configuration Program.

TCK

The electronic clock signal which times data on the TAP data lines TMS, TDI, and TDO.

TDI

The electronic signal input to a TAP controller from the data source (upstream). Usually, this is seen connecting the J-Link Interface Unit to the first TAP controller.

TDO

The electronic signal output from a TAP controller to the data sink (downstream). Usually, this is seen connecting the last TAP controller to the J-Link Interface Unit.

Test Access Port (TAP)

The port used to access a device's TAP Controller. Comprises TCK, TMS, TDI, TDO, and nTRST (optional).

Transistor-transistor logic (TTL)

A type of logic design in which two bipolar transistors drive the logic output to one or zero. LSI and VLSI logic often used TTL with HIGH logic level approaching +5V and LOW approaching 0V.

W

Word

A 32-bit unit of information. Contents are taken as being an unsigned integer unless otherwise stated.