NXP i.MX RT700

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Revision as of 11:00, 7 April 2025 by Matthias (talk | contribs) (Created page with "The '''NXP i.MXRT700''' are multi-core MCUs consisting of two Cortex-M33 and one RISC-V cores. __TOC__ ==Flash Banks== ===QSPI Flash=== QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.<br> {| class="seggertable" |- ! Bank !! Base address !! Maximum size |- | XSPI1 || 0x08000000 || 128 MB |- | XSPI0 || 0x28000000 || 128...")
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The NXP i.MXRT700 are multi-core MCUs consisting of two Cortex-M33 and one RISC-V cores.

Flash Banks

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.

Bank Base address Maximum size
XSPI1 0x08000000 128 MB
XSPI0 0x28000000 128 MB

Watchdog Handling

  • The watchdogs WWDT0 and WWDT1 are fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MXRT700 family comes with multiple cores, of which the following are supported:

Core J-Link Support
Cortex-M33 (CPU0) YES.png
Cortex-M33 (CPU1) YES.png
RISC-V (EZH-V) YES.png

Device Specific Handling

Connect

Debug access is enabled through debug mailbox.

Reset

The device uses custom reset to ensure that the boot ROM is executed. Afterwards debug access is reenabled.

Evaluation Boards

Example Application

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