J-Trace PRO RISC-V: Difference between revisions
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| SWD interface ||style="text-align:center;"| {{YES}} || V3 | | SWD interface ||style="text-align:center;"| {{YES}} || V3 | ||
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| SWO interface ||style="text-align:center;"| {{ | | SWO interface ||style="text-align:center;"| {{NO}} || | ||
|- | |- | ||
| ETB Trace Cortex ||style="text-align:center;"| {{ | | ETB Trace Cortex ||style="text-align:center;"| {{NO}} || V3 | ||
|- | |- | ||
| ETM Trace Cortex ||style="text-align:center;"| {{ | | ETM Trace Cortex ||style="text-align:center;"| {{NO|| V3 | ||
|- | |- | ||
| PTM Trace Cortex ||style="text-align:center;"| {{YES}} || V3 | | PTM Trace Cortex ||style="text-align:center;"| {{NO}} || V3 | ||
|- | |||
| N-Trace BTM RISC-V ||style="text-align:center;"| {{YES}} || V3 | |||
|- | |- | ||
| Streaming Trace ||style="text-align:center;"| {{YES}} || V3 | | Streaming Trace ||style="text-align:center;"| {{YES}} || V3 | ||
|- | |- | ||
| VCOM | | VCOM ||style="text-align:center;"| {{NO}} || | ||
|- | |- | ||
| Memory Stop mode support ||style="text-align:center;"| {{YES}} || V3 | | Memory Stop mode support ||style="text-align:center;"| {{YES}} || V3 | ||
|- | |- | ||
| Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{ | | Cortex-M Monitor Mode debugging ||style="text-align:center;"| {{NO}} || V3 | ||
|- | |- | ||
| 5 V Target Supply ||style="text-align:center;"| {{YES}} || V3 | | 5 V Target Supply ||style="text-align:center;"| {{YES}} || V3 | ||
|- | |- | ||
| SWD Multi-Drop ||style="text-align:center;"| {{ | | SWD Multi-Drop ||style="text-align:center;"| {{NO}} || V3 | ||
|- | |- | ||
| CMSIS-DAP v1 (HID) mode ||style="text-align:center;"| {{NO}} || | | CMSIS-DAP v1 (HID) mode ||style="text-align:center;"| {{NO}} || | ||
Revision as of 10:51, 17 July 2025
This page contains the general, specifications as well as an overview of supported software features of the SEGGER J-Trace PRO RISC-V.
For information on the mechanical and electrical specifications as well as an overview of hardware features refer to Hardware Models.
Hardware Models
Legacy
Hardware Features
| Feature | Supported | Since |
|---|---|---|
| USB 2.0 Hi-Speed |  |
V3 |
| USB 3.0 SuperSpeed | |
V3 |
| WinUSB | |
V3 |
| Gigabit-Ethernet | |
V3 |
| cJTAG interface | |
V3 |
| cJTAG interface without/buggy KEEPER logic | |
V3 |
| JTAG interface | |
V3 |
| SWD interface | |
V3 |
| SWO interface |  |
|
| ETB Trace Cortex | |
V3 |
| ETM Trace Cortex | {{NO | V3 |
| PTM Trace Cortex | |
V3 |
| N-Trace BTM RISC-V | |
V3 |
| Streaming Trace | |
V3 |
| VCOM | |
|
| Memory Stop mode support | |
V3 |
| Cortex-M Monitor Mode debugging | |
V3 |
| 5 V Target Supply | |
V3 |
| SWD Multi-Drop | |
V3 |
| CMSIS-DAP v1 (HID) mode | |
Supported cores
J-Trace provides debugging support for the following cores.
Note:
If you are interested in J-Trace support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
If you are interested in J-Trace support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
| Core | Supported | Since |
|---|---|---|
| RISC-V | ||
| RV32 | |
V3 |
| RV64 | |
V3 |