Xilinx Zynq UltraScalePlus

The Xilinx Zynq UltraScale+ is a multi-processor system on chip, that contains up to 4 ARM Cortex-A53 application processor cores, 2 ARM Cortex-R5 real-time processor cores and user-programmagble logic (FGPA). It can optionally include ARM Mali-400MP2 graphical processor, H.264/H.265 Video Codec, RF and digital front-end subsystem.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The Zynq UltraScale+ family comes with a variety of multi-core options.
The device contains 2 Microblaze cores (CSU and PMU) that implements security and platform management features. These cores are responsible for boot and system configuration processes.

Core	J-Link Support
4x Cortex-A53
2x Cortex-R5
1x Microblaze CSU
1x Microblaze PMU
1x Mali GPU

In below, the debug related multi-core behavior of the J-Link is described for each core:

Cortex-A53

Init/Setup

In order to connect to and debug one of the available Cortex-A53 on the UltraScale+ series, an UltraScale+ device with XCZU..._A53_n must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website.

Reset

When connecting to the Cortex-A53, J-Link will try to attach to a running target, otherwise it will reset the core and halt it via vector catch. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-A53 core it is connected to. No peripherals or other cores will be reset. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset.

Attach

Attach supported.

Cortex-R5

Init/Setup

In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with XCZU..._R5_n must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website. Dual/Split mode is supported only if not attaching to a running target.

Reset

When connecting to the Cortex-R5, J-Link will try to attach to a running target, otherwise it will reset the core and halt it via vector catch. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-A53 core it is connected to. No peripherals or other cores will be reset. When issuing a reset via J-Link (e.g. by hitting the reset button in the IDE), J-Link will only reset the Cortex-R5 core it is connected to. No peripherals or other cores will be reset.

Attach

Attach is supported.

Limitations

J-Link only supports JTAG-boot mode, as ARM DAP access can be enabled externaly. Cortex-A53 and Cortex-R5 are held in reset by default in this mode.
JTAG access to the ARM DAP is enabled by J-Link before connecting to the target.
J-Link supports only connection via the PS JTAG interface.

Example Application

The following projects are simple Hello world applications, loaded into the OCMRAM memory of the Zynq UltraScale+.

Cortex-A53

• File:AMD Xilinx EK-U1-ZCU106-G A53 0 TestProject ES V814.zip

Cortex-R5

• File:AMD Xilinx EK-U1-ZCU106-G R5 0 TestProject ES V814.zip
  
• File:AMD Xilinx EK-U1-ZCU106-G R5 1 TestProject ES V814.zip

Tracing on Xilinx Zynq UltraScale+

This section describes how to get started with trace on the Xilinx Zynq UltraScale+ MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

Some of the examples are shipped with a compiled .JLinkScriptfile (extension .pex), should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Minimum requirements

In order to use trace on the Xilinx Zynq UltraScale+ MCU devices, the following minimum requirements have to be met:

• J-Link software version V8.10a or later
• Ozone V3.34a or later (if streaming trace and / or the sample project from below shall be used)
• J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
• J-Link Plus V12 or later for TMC/ETB trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V8.14a. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Trace buffer (TMC/ETB)

Buffer tracing is supported out-of-the-box for all Cortex-A53 and Cortex-R5 cores on the chip. Booting the cores correctly and powering them is user responsibility and will not be handled by the debug/trace probe.

Streaming Trace

For pin tracing to work the trace pins must be routed to the trace header first. It is user responsibility to do so. On his device the trace pins are routed through the FPGA fabric. For more information on this see the Xilinx device reference manual.

Once the device is fully booted and the pins enabled you will need to use the pex files below in your project to enable trace. How to use the pex files in your project is explained here.

Core A53_0

File:Xilinx UltraScale A53 0 TraceExample.pex

Core A53_1

File:Xilinx UltraScale A53 1 TraceExample.pex

Core A53_2

File:Xilinx UltraScale A53 2 TraceExample.pex

Core A53_3

File:Xilinx UltraScale A53 3 TraceExample.pex

Core R5_0

File:Xilinx UltraScale R5 0 TraceExample.pex

Core R5_1

File:Xilinx UltraScale R5 1 TraceExample.pex