NXP i.MX RT700: Difference between revisions
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(Mentioned flash programming for XSPI1 and XSPI0 in secure address space.) |
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===QSPI Flash=== | ===QSPI Flash=== | ||
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> | ||
For a complete list of supported flash devices, please refer to the [https://www.segger.com/products/debug-probes/j-link/technology/cpus-and-devices/supported-spi-flashes/ Supported SPI Flashes] page on our website. | |||
{| class="seggertable" | {| class="seggertable" | ||
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|- | |- | ||
| XSPI1 || 0x08000000 || 128 MB | | XSPI1 || 0x08000000 || 128 MB | ||
|- | |||
| XSPI1 (secure) || 0x18000000 || 128 MB | |||
|- | |- | ||
| XSPI0 || 0x28000000 || 128 MB | | XSPI0 || 0x28000000 || 128 MB | ||
|- | |||
| XSPI0 (secure) || 0x38000000 || 128 MB | |||
|} | |} | ||
Latest revision as of 15:11, 15 August 2025
The NXP i.MXRT700 are multi-core MCUs consisting of two Cortex-M33 and one RISC-V cores.
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
For a complete list of supported flash devices, please refer to the Supported SPI Flashes page on our website.
| Bank | Base address | Maximum size |
|---|---|---|
| XSPI1 | 0x08000000 | 128 MB |
| XSPI1 (secure) | 0x18000000 | 128 MB |
| XSPI0 | 0x28000000 | 128 MB |
| XSPI0 (secure) | 0x38000000 | 128 MB |
Watchdog Handling
- The watchdogs WWDT0 and WWDT1 are fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The i.MXRT700 family comes with multiple cores, of which the following are supported:
| Core | J-Link Support |
|---|---|
| Cortex-M33 (CPU0) | 
|
| Cortex-M33 (CPU1) |
|
| RISC-V (EZH-V) |
|
Device Specific Handling
Connect
Debug access is enabled through debug mailbox.
Reset
The device uses custom reset to ensure that the boot ROM is executed. Afterwards debug access is reenabled.