J-Link LITE Cortex-M: Difference between revisions
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(Created page with "This page contains the general, specifications as well as an overview of supported software features of the SEGGER '''J-Link LITE Cortex-M'''. <br> For information on the mechanical and electrical specifications as well as an overview of hardware features refer to Hardware Models. __TOC__ == Hardware Models == * J-Link LITE Cortex-M V9 === Legacy === * J-Link LITE Cortex-M V8 == Software Features == {| class="seggertable" |- ! Feature...") |
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| Cortex-A76 ||style="text-align:center;"| {{NO}} || | |||
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| Cortex-M0 ||style="text-align:center;"| {{YES}} || V8 | | Cortex-M0 ||style="text-align:center;"| {{YES}} || V8 |
Latest revision as of 11:00, 30 July 2025
This page contains the general, specifications as well as an overview of supported software features of the SEGGER J-Link LITE Cortex-M.
For information on the mechanical and electrical specifications as well as an overview of hardware features refer to Hardware Models.
Hardware Models
Legacy
Software Features
Feature | Supported | since |
---|---|---|
USB 2.0 Full Speed | ![]() |
V8 |
USB 2.0 Hi-Speed | ![]() |
|
WinUSB | ![]() |
|
JTAG interface | ![]() |
V8 |
cJTAG interface | ![]() |
|
cJTAG interface without/buggy KEEPER logic | ![]() |
|
SWD interface | ![]() |
V8 |
SWO interface | ![]() |
V8 |
SPI interface | ![]() |
|
QSPI interface | ![]() |
|
Microchip ICSP interface | ![]() |
|
Renesas FINE interface | ![]() |
|
SiLabs C2 2-wire interface | ![]() |
|
ETB Trace ARM7/9 | ![]() |
|
ETB Trace Cortex-M | ![]() |
V8 |
ETB Trace Cortex-A/R | ![]() |
|
ETM Trace Cortex-M | ![]() |
|
VCOM* | ![]() |
|
Memory Stop mode support | ![]() |
V9 |
Cortex-M Monitor Mode debugging | ![]() |
|
SWD Multi-Drop | ![]() |
|
CMSIS-DAP v1 (HID) mode | ![]() |
|
USB Web Server | ![]() |
Notes:
*On J-Links, VCOM is a "USB to serial" bridge that connects the PC to a UART of the target, so you can communicate with your target application.
*On J-Links, VCOM is a "USB to serial" bridge that connects the PC to a UART of the target, so you can communicate with your target application.
Supported cores
J-Link provides debugging support for the following cores.
Note:
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
If you are interested in J-Link support for a core that is not listed here, please feel free to request support via the SEGGER support ticket system.
Core | Supported | since | ||
---|---|---|---|---|
ARM legacy Cores | ||||
ARM7 | ![]() |
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ARM9 | ![]() |
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ARM11 | ![]() |
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ARM Cortex Cores | ||||
Cortex-A5 | ![]() |
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Cortex-A7 | ![]() |
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Cortex-A8 | ![]() |
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Cortex-A9 | ![]() |
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Cortex-A12 | ![]() |
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Cortex-A15 | ![]() |
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Cortex-A17 | ![]() |
|||
Cortex-A53 | ![]() |
|||
Cortex-A55 | ![]() |
|||
Cortex-A57 | ![]() |
|||
Cortex-A72 | ![]() |
|||
Cortex-A76 | ![]() |
|||
Cortex-M0 | ![]() |
V8 | ||
Cortex-M0+ | ![]() |
V8 | ||
Cortex-M1 | ![]() |
V8 | ||
Cortex-M3 | ![]() |
V8 | ||
Cortex-M4 | ![]() |
V8 | ||
Cortex-M7 | ![]() |
V9 | ||
Cortex-M23 | ![]() |
V9 | ||
Cortex-M33 | ![]() |
V9 | ||
Cortex-R4 | ![]() |
|||
Cortex-R5 | ![]() |
|||
Cortex-R8 | ![]() |
|||
SC000 (M0 secure) | ![]() |
V8 | ||
SC300 (M3 secure) | ![]() |
V8 | ||
RISC-V | ||||
RV32 | ![]() |
|||
RV64 | ![]() |
|||
Microchip PIC32 | ||||
PIC32MX | ![]() |
|||
PIC32MZ | ![]() |
|||
SiLabs 8051 | ||||
EFM8 | ![]() |
|||
Renesas RX | ||||
RX110 | ![]() |
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RX111 | ![]() |
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RX210 | ![]() |
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RX21A | ![]() |
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RX220 | ![]() |
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RX610 | ![]() |
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RX621 | ![]() |
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RX62G | ![]() |
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RX62G | ![]() |
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RX62N | ![]() |
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RX62T | ![]() |
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RX630 | ![]() |
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RX631 | ![]() |
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RX63N | ![]() |
|||
RX63T | ![]() |
|||
RX64M | ![]() |