Tongxin THA6 Gen 2: Difference between revisions

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(Created page with "Category:Device families The '''Tongxin THA6 Gen 2''' device family are Cortex-R52 based microcontrollers. __TOC__ ==Flash Banks== {{:Template:FlashBankTable | FlashBanks= {{:Template:FlashBankTableRow | BankName=PFLASH0<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader= {{:Template:FlashLoader | Name=Default | Size=3 MB }} }} {{:Template:FlashBankTableRow | BankName=PFLASH1<ref name="FootNote1" >Ena...")
 
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{{:Template:FlashBankTableRow | BankName=PFLASH0<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=PFLASH0<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH0 NVR<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x09800000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=16 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH1<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08300000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=PFLASH1<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x08300000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH1 NVR<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x09804000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=16 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH0 NVR (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x41C00000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=16 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x40700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH1 NVR (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x41C04000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=16 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS memory)<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x44000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS memory)<ref name="FootNote1" >Enabled by default</ref> | BaseAddress=0x44000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=512 KB }}
{{:Template:FlashLoader | Name=Default | Size=512 KB }}
}}
{{:Template:FlashBankTableRow | BankName=DFLASH0 NVR (MBUS memory)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x44400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=32 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=PFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH0 NVR (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x91C00000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=16 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=PFLASH1 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x90700000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
{{:Template:FlashLoader | Name=Default | Size=3 MB }}
}}
{{:Template:FlashBankTableRow | BankName=PFLASH1 NVR (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x91C04000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=16 KB }}
}}
}}
{{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x94000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashBankTableRow | BankName=DFLASH0 (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x94000000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=512 KB }}
{{:Template:FlashLoader | Name=Default | Size=512 KB }}
}}
{{:Template:FlashBankTableRow | BankName=DFLASH0 NVR (MBUS device)<ref name="FootNote2" >Disabled by default</ref> | BaseAddress=0x94400000 | JLinkSupport=yes | NumOfLoaders=1 | Loader=
{{:Template:FlashLoader | Name=Default | Size=32 KB }}
}}
}}
}}
}}
<references />
<references />
==ECC RAM [OPTIONAL]==
*Describe ECC RAM restriction here.
==Vector Table Remap [OPTIONAL]==
*Describe Vector Table Remap here..


==Watchdog Handling==
==Watchdog Handling==
*The device does not have a watchdog.
*The device has a watchdog IWDT.  
*The device has a watchdog [WATCHDOGNAME].  
*The watchdog is fed during flash programming.
*The watchdog is fed during flash programming.
*If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
*The watchdog can be configured in normal or window mode.
** If it is configured in normal mode the watchdog is feed during flash programming.
** If it is configured in window mode the watchdog is feed during flash programming.
** If it is configured in window mode the watchdog is '''not''' feed.


==Multi-Core Support [OPTIONAL]==
==Multi-Core Support==
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br>
The [DeviceFamily]family comes with a variety of multi-core options.<br>
The THA6 family comes with a Cortex-R52 primary core and up to three Cortex-R52 secondary cores.<br>
Some devices from this family feature a secondary core which is disabled after reset / by default.<br>
Some of the are available with enabled ''lockstep'' mode, only. <br>
{| class="seggertable"
{| class="seggertable"
|-
|-
! Core || J-Link Support
! Core || J-Link Support
|-
|-
| [CORE_NAME] || style="text-align:center;"| {{YES}} / {{NO}}  
| Cortex-R52 CPU0 || style="text-align:center;"| {{YES}}
|-
| Cortex-R52 CPU1 || style="text-align:center;"| {{YES}}
|-
| Cortex-R52 CPU2 || style="text-align:center;"| {{YES}}
|-
| Cortex-R52 CPU3 || style="text-align:center;"| {{YES}}
|}
|}


Line 65: Line 80:
===Main core===
===Main core===
====Init/Setup====
====Init/Setup====
*Initializes the ECC RAM, see [[XXX | XXX]]
*Secure Debug:
*Enables debugging
**Authentication levels EL1 and EL2 are supported.
**Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
* Halt timer configuration:
** Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.
====Reset====
====Reset====
*Device specific reset is performed, see [[XXX | XXX]]
*The device uses custom reset:
**Sets reset catch so that CPU is halted immediately after reset
**Performs reset via EDPRCR register
**Ensures that debug power domain and system power domain are powered up
**Powers core if necessary
**Enables debug mode if necessary
**Clears reset catch
====Attach====
====Attach====
*Attach is not supported because the J-Link initializes certain RAM regions by default
*Attach is supported
 
===Secondary core(s)===
===Secondary core(s)===
====Init/Setup====
====Init/Setup====
*If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
*Secure Debug:
*If the secondary core is not enabled yet, it will be enabled / release from reset
**Authentication levels EL1 and EL2 are supported.
**Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
* Halt timer configuration:
** Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.
====Reset====
====Reset====
No reset is performed.
*The device uses custom reset:
**Sets reset catch so that CPU is halted immediately after reset
**Performs reset via EDPRCR register
**Ensures that debug power domain and system power domain are powered up
**Powers core if necessary
**Enables debug mode if necessary
**Clears reset catch
====Attach====
====Attach====
*Attach is supported / desired
*Attach is supported
 
==Device Specific Handling==
===Connect===
===Reset===
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]].
*The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]].
*The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]].
*The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]].
*The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]].
*The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]].
*The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]].
*The device uses custom reset:.....
 
==Limitations==
===Dual Core Support===
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
===Attach===
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
===Security===


==Evaluation Boards==
==Evaluation Boards==
*[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]]
*[[Tongxin THA6206-KIT-V1.0]]


==Example Application==
==Example Application==
*[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]]
*[[Tongxin THA6206-KIT-V1.0#Example_Project | Tongxin THA6206-KIT-V1.0]]
 
== Tracing ==
The following trace example projects are available:
* [Link to Board Article1]
* [Link to Board Article2]
* ...

Latest revision as of 09:38, 9 July 2025

The Tongxin THA6 Gen 2 device family are Cortex-R52 based microcontrollers.

Flash Banks

Flash Bank Base address J-Link Support Loader
Name Size
PFLASH0[1] 0x08000000 YES.png Default 3 MB
PFLASH0 NVR[2] 0x09800000 YES.png Default 16 KB
PFLASH1[1] 0x08300000 YES.png Default 3 MB
PFLASH1 NVR[2] 0x09804000 YES.png Default 16 KB
PFLASH0 (MBUS memory)[2] 0x40400000 YES.png Default 3 MB
PFLASH0 NVR (MBUS memory)[2] 0x41C00000 YES.png Default 16 KB
PFLASH1 (MBUS memory)[2] 0x40700000 YES.png Default 3 MB
PFLASH1 NVR (MBUS memory)[2] 0x41C04000 YES.png Default 16 KB
DFLASH0 (MBUS memory)[1] 0x44000000 YES.png Default 512 KB
DFLASH0 NVR (MBUS memory)[2] 0x44400000 YES.png Default 32 KB
PFLASH0 (MBUS device)[2] 0x90400000 YES.png Default 3 MB
PFLASH0 NVR (MBUS device)[2] 0x91C00000 YES.png Default 16 KB
PFLASH1 (MBUS device)[2] 0x90700000 YES.png Default 3 MB
PFLASH1 NVR (MBUS device)[2] 0x91C04000 YES.png Default 16 KB
DFLASH0 (MBUS device)[2] 0x94000000 YES.png Default 512 KB
DFLASH0 NVR (MBUS device)[2] 0x94400000 YES.png Default 32 KB
  1. ↑ 1.0 1.1 1.2 Enabled by default
  2. ↑ 2.00 2.01 2.02 2.03 2.04 2.05 2.06 2.07 2.08 2.09 2.10 2.11 2.12 Disabled by default

Watchdog Handling

  • The device has a watchdog IWDT.
  • The watchdog is fed during flash programming.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The THA6 family comes with a Cortex-R52 primary core and up to three Cortex-R52 secondary cores.

Core J-Link Support
Cortex-R52 CPU0 YES.png
Cortex-R52 CPU1 YES.png
Cortex-R52 CPU2 YES.png
Cortex-R52 CPU3 YES.png

In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

  • Secure Debug:
    • Authentication levels EL1 and EL2 are supported.
    • Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
  • Halt timer configuration:
    • Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.

Reset

  • The device uses custom reset:
    • Sets reset catch so that CPU is halted immediately after reset
    • Performs reset via EDPRCR register
    • Ensures that debug power domain and system power domain are powered up
    • Powers core if necessary
    • Enables debug mode if necessary
    • Clears reset catch

Attach

  • Attach is supported

Secondary core(s)

Init/Setup

  • Secure Debug:
    • Authentication levels EL1 and EL2 are supported.
    • Only the default password (all bytes set to 0xFF) is supported. If you need to unlock the device using a custom password, please contact us through our support ticket system.
  • Halt timer configuration:
    • Corsight CTI is configured to halt the following timers simultaneously with the R52 cores: STM, IWDT, SAFEWDT, CPUWDTn and BASETIMERn.

Reset

  • The device uses custom reset:
    • Sets reset catch so that CPU is halted immediately after reset
    • Performs reset via EDPRCR register
    • Ensures that debug power domain and system power domain are powered up
    • Powers core if necessary
    • Enables debug mode if necessary
    • Clears reset catch

Attach

  • Attach is supported

Evaluation Boards

Example Application

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